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C++BOLD Example Design: IROD

// THIS FILE IS IN THE PUBLIC DOMAIN.
// IT IS PROVIDED AS IS WITHOUT WARRANTY OF ANY KIND, EITHER EXPRESSED OR IMPLIED, INCLUDING, BUT
// NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE.
 
#ifndef _T_VMEBuffersH_
#define _T_VMEBuffersH_
 
#include "sn74abte16245.h"
#include "74f07.h"
#include "rod_clones.h"
 
class CM_VMEBuffers : public TModule {
public:
 
  //Define ports
  port D;               //Buffered VME Data Bus
  port VMED;            //Raw VME Data Bus
  port DBUFOE_N;        //Data Bus Buffer Output Enable
  port DBUFDIR;         //Data Bus Buffer Direction Signal
  port A;               //Buffered VME Address Bus
  port VMEA;            //Raw VME Data Bus
  port ABUFDIR;         //Address Bus Buffer Direction Signal
  port ABUFOE_N;        //Address Bus Buffer Output Enable
  port IBUFOE_N;        //Input Buffer Output Enable
 
  port VPC;             //VCC Pre-charge from VME Backplane
  port DTACK_N;         //Buffered VME DTACK Signal - used in VME Bus transactions
  port VME_DTACK_N;     //Raw VME DTACK Signal
  port BERR_N;          //Buffered VME Bus Error Signal (Wired but unused)
  port VME_BERR_N;      //Raw VME Bus Error Signal
  port IACKOUT_N;       //Buffered VME Interrupt Acknowledge Out (Part of Interrupt Daisy Chain)
  port VME_IACKOUT_N;   //Raw VME Interrupt Acknowledge Out
  port IRQ;             //Buffered VME Interrupt Request Bus (7 Interrupt Requests)
  port VME_IRQ;         //Raw VME Interrupt Request Bus
  port VCC5;            //5-Volt VCC
  port GND;
  port AM;              //Buffered VME Address Modifier Signal
  port VME_AM;          //Raw VME Address Modifier
  port AS_N;            //Buffered VME Address Strobe
  port VME_AS_N;        //Raw VME Address Strobe
  port DS0_N;           //Buffered VME Data Strobe 0
  port VME_DS0_N;       //Raw VME Data Strobe 0
  port DS1_N;           //Buffered VME Data Strobe 1
  port VME_DS1_N;       //Raw VME Data Strobe 1
  port WRITE_N;         //Buffered VME Write (used to indicate a Write transaction)
  port VME_WRITE_N;     //Raw VME Write
  port SYSRESET_N;      //Buffered VME System Reset
  port VME_SYSRESET_N;  //Raw VME System Reset
  port IACK_N;          //Buffered VME Interrupt Acknowledge
  port VME_IACK_N;      //Raw VME Interrupt Acknowledge
  port IACKIN_N;        //Buffered VME Interrupt Acknowledge in (Part of Interrupt Daisy Chain)
  port VME_IACKIN_N;    //Raw VME Interrupt Acknowledge In
 
  //Instantiate parts
  CP_SN74ABTE16245  DataBuffer15_00;
  CP_SN74ABTE16245  DataBuffer31_16;
  CP_SN74ABTE16245  AddrBuffer15_01;
  CP_SN74ABTE16245  AddrBuffer23_16;
  CP_SN74ABTE16245  AddrBuffer31_24;
  CP_74F07          CntlBuffer1;
  CP_74F07          CntlBuffer2;
  CP_SN74ABTE16245  InptBuffer;
 
  CP_R360           VPC_Res_AddrBuf;          //Series resistors on VPC
  CP_R360           VPC_Res_DataBuf;
  CP_R360           VPC_Res_InptBuf;
  CP_R0             OE_Res_AddrBuf;   // 0-Ohm resistors to allow for interchangeability between
  CP_R0             OE_Res_DataBuf;   // abte16245 and abt16245.  abt16245 has an OE_N instead of VCCBIAS.
  CP_R0             OE_Res_InptBuf;
  CP_R0             Pullup_DIR_InptBuf;       // DIR has reversed meanings between abte16245 and abt16245. Allow
  CP_R0             Pulldown_DIR_InptBuf;     // for interchangeability between the two.
 
  CP_R4_7K          Pullup_OE_AddrBuf;        // pullups to VPC (via series resistor) --> all buffers high impedance unless VCC5 and VCC are up
  CP_R4_7K          Pullup_OE_DataBuf;
  CP_R4_7K          Pullup_OE_InptBuf;
  CP_R110           Pullup_IACKOUT;           // use pullup to "drive" VME_IACKOUT_N high with open-collector driver
  CP_EXB2HV222JV    Pullup_CtrlBuf1;          // 2.2K pullups for CntlBuffer inputs
  CP_EXB2HV222JV    Pullup_CtrlBuf2;
 
 
  virtual void Register() {  //Register function
 
    //Register all ports
    regb( D, 31, 0 );
    regb( VMED, 31, 0 );
    reg ( DBUFOE_N );
    reg ( DBUFDIR );
    regb( A, 31, 0 );
    regb( VMEA, 31, 0 );
    reg ( ABUFDIR );
    reg ( ABUFOE_N );
    reg ( IBUFOE_N );
    reg ( VPC );
    reg ( DTACK_N );
    reg ( VME_DTACK_N );
    reg ( BERR_N );
    reg ( VME_BERR_N );
    reg ( IACKOUT_N );
    reg ( VME_IACKOUT_N );
    regb( IRQ, 7, 1 );
    regb( VME_IRQ, 7, 1 );
    reg ( VCC5 );
    reg ( GND );
    regb( AM, 5, 0 );
    regb( VME_AM, 5, 0 );
    reg ( AS_N );
    reg ( VME_AS_N );
    reg ( DS0_N );
    reg ( VME_DS0_N );
    reg ( DS1_N );
    reg ( VME_DS1_N );
    reg ( WRITE_N );
    reg ( VME_WRITE_N );
    reg ( SYSRESET_N );
    reg ( VME_SYSRESET_N );
    reg ( IACK_N );
    reg ( VME_IACK_N );
    reg ( IACKIN_N );
    reg ( VME_IACKIN_N );
 
    //Register all instantiated parts and modules
    reg( DataBuffer15_00 );
    reg( DataBuffer31_16 );
    reg( AddrBuffer15_01 );
    reg( AddrBuffer23_16 );
    reg( AddrBuffer31_24 );
    reg( CntlBuffer1 );
    reg( CntlBuffer2 );
    reg( InptBuffer );
 
    reg( VPC_Res_AddrBuf );
    reg( VPC_Res_DataBuf );
    reg( VPC_Res_InptBuf );
    reg( OE_Res_AddrBuf  );
    reg( OE_Res_DataBuf  );
    reg( OE_Res_InptBuf  );
    reg( Pullup_DIR_InptBuf   );
    reg( Pulldown_DIR_InptBuf );
 
    reg( Pullup_OE_AddrBuf );
    reg( Pullup_OE_DataBuf );
    reg( Pullup_OE_InptBuf );
    reg( Pullup_IACKOUT    );
    reg( Pullup_CtrlBuf1   );
    reg( Pullup_CtrlBuf2   );
  }
 
  virtual void Connect() {
 
    D(    15,  0 )   << DataBuffer15_00.B;
    D(    31, 16 )   << DataBuffer31_16.B;
    VMED( 15,  0 )   << DataBuffer15_00.A;
    VMED( 31, 16 )   << DataBuffer31_16.A;
 
    // CM_VME_Interface uses A( 0 ) and VMEA( 0 ) for LWORD_N
    // for best routing, A( 0 ) is now on AddrBuffer23_16
    A(         0 )   << AddrBuffer23_16.B( 8 );
    VMEA(      0 )   << AddrBuffer23_16.A( 8 );
 
    A(    15,  1 )   << AddrBuffer15_01.B( 0, 14 );   // order reversed for better layout
    A(    23, 16 )   << AddrBuffer23_16.B( 0,  7 );   // order reversed for better layout
    A(    31, 24 )   << AddrBuffer31_24.B( 7,  0 );
 
    VMEA( 15,  1 )   << AddrBuffer15_01.A( 0, 14 );   // order reversed for better layout
    VMEA( 23, 16 )   << AddrBuffer23_16.A( 0,  7 );   // order reversed for better layout
    VMEA( 31, 24 )   << AddrBuffer31_24.A( 7,  0);
 
    DBUFOE_N         << DataBuffer15_00.OE_N << DataBuffer31_16.OE_N;
    ABUFOE_N         << AddrBuffer15_01.OE_N << AddrBuffer23_16.OE_N << AddrBuffer31_24.OE_N;
    IBUFOE_N         <<      InptBuffer.OE_N;  // always asserted when VCC is valid, pulled to VCC5 when VCC < 2.5V
 
    DBUFDIR          << DataBuffer15_00.DIR  << DataBuffer31_16.DIR;
    ABUFDIR          << AddrBuffer15_01.DIR  << AddrBuffer23_16.DIR  << AddrBuffer31_24.DIR;
    "IBUFDIR"        <<      InptBuffer.DIR;   // for readable net name
 
// abte16245 DIR has opposite meaning of abt16245 DIR
// provide both pullup and pulldown to allow substitution of abt16245 for abte16245
    GND  ^ Pulldown_DIR_InptBuf ^ InptBuffer.DIR;   // install for ABTE
    VCC5 ^   Pullup_DIR_InptBuf ^ InptBuffer.DIR;   // install for ABT
 
 
// provide both OE_N and VPC series resistors to allow substitution of abt16245 for abte16245
//          abte16245   abt16245
// pin 48:   VCCBIAS       1OE*      CP_SN74ABTE16245 pin name:  "VCCBIAS"
// pin 25:    OE*          2OE*      CP_SN74ABTE16245 pin name:  "OE_N"
 
// ABTE:  install VPC_Res...
    VPC  ^ VPC_Res_AddrBuf ^  "OE_N_BIAS_A"  <<  AddrBuffer15_01.VCCBIAS  <<  AddrBuffer23_16.VCCBIAS << AddrBuffer31_24.VCCBIAS;
    VPC  ^ VPC_Res_DataBuf ^  "OE_N_BIAS_D"  <<  DataBuffer15_00.VCCBIAS  <<  DataBuffer31_16.VCCBIAS;
    VPC  ^ VPC_Res_InptBuf ^  "OE_N_BIAS_C"  <<       InptBuffer.VCCBIAS;
 
// ABT:  install OE_Res...
    "OE_N_BIAS_A"  ^ OE_Res_AddrBuf ^  ABUFOE_N;
    "OE_N_BIAS_D"  ^ OE_Res_DataBuf ^  DBUFOE_N;
    "OE_N_BIAS_C"  ^ OE_Res_InptBuf ^  GND;
 
 
// pullups to VCC5 --> all buffers high impedance unless VCC (3.3V) is up
    ABUFOE_N  ^ Pullup_OE_AddrBuf ^  VCC5;
    DBUFOE_N  ^ Pullup_OE_DataBuf ^  VCC5;
    IBUFOE_N  ^ Pullup_OE_InptBuf ^  VCC5;
 
// pull up inputs to CntlBuffer's -> inactive when VCC and/or VCC5 is not up
    merge( VCC5, Pullup_CtrlBuf1.A );
    merge( VCC5, Pullup_CtrlBuf2.A );
    merge( "/NC", Pullup_CtrlBuf1.B( 7, 6 ) );
    merge( "/NC", Pullup_CtrlBuf2.B( 7, 6 ) );
                                                                         // signal order below rough corresponds with J1/P1, J2/P2 layout
    "UNUSED"        << CntlBuffer1.A( 0 )  <<  Pullup_CtrlBuf1.B( 0 );   // 0 5 1 4 2 3 is the vertical layout order, top to bottom, of 74F07 I/O
    BERR_N          << CntlBuffer1.A( 5 )  <<  Pullup_CtrlBuf1.B( 1 );
    DTACK_N         << CntlBuffer1.A( 1 )  <<  Pullup_CtrlBuf1.B( 2 );
    IACKOUT_N       << CntlBuffer1.A( 4 )  <<  Pullup_CtrlBuf1.B( 3 );
    IRQ( 7 )        << CntlBuffer1.A( 2 )  <<  Pullup_CtrlBuf1.B( 4 );
    IRQ( 6 )        << CntlBuffer1.A( 3 )  <<  Pullup_CtrlBuf1.B( 5 );
 
    IRQ( 5 )        << CntlBuffer2.A( 0 )  <<  Pullup_CtrlBuf2.B( 0 );
    IRQ( 4 )        << CntlBuffer2.A( 5 )  <<  Pullup_CtrlBuf2.B( 1 );
    IRQ( 3 )        << CntlBuffer2.A( 1 )  <<  Pullup_CtrlBuf2.B( 2 );
    IRQ( 2 )        << CntlBuffer2.A( 4 )  <<  Pullup_CtrlBuf2.B( 3 );
    IRQ( 1 )        << CntlBuffer2.A( 2 )  <<  Pullup_CtrlBuf2.B( 4 );
    "UNUSED_RETRY"  << CntlBuffer2.A( 3 )  <<  Pullup_CtrlBuf2.B( 5 );   // formerly RETRY_N (at top of J2/P2 --> nearest to IRQ(1))
 
    "/NC"           << CntlBuffer1.Y( 0 );
    VME_BERR_N      << CntlBuffer1.Y( 5 );
    VME_DTACK_N     << CntlBuffer1.Y( 1 );
    VME_IACKOUT_N   << CntlBuffer1.Y( 4 )   ^ Pullup_IACKOUT ^  VCC5;   // "totem pole" signal, must be "driven" high
    VME_IRQ( 7 )    << CntlBuffer1.Y( 2 );
    VME_IRQ( 6 )    << CntlBuffer1.Y( 3 );
 
    VME_IRQ( 5 )    << CntlBuffer2.Y( 0 );
    VME_IRQ( 4 )    << CntlBuffer2.Y( 5 );
    VME_IRQ( 3 )    << CntlBuffer2.Y( 1 );
    VME_IRQ( 2 )    << CntlBuffer2.Y( 4 );
    VME_IRQ( 1 )    << CntlBuffer2.Y( 2 );
    "/NC"           << CntlBuffer2.Y( 3 );   // formerly VME_RETRY_N
 
    SYSRESET_N      << InptBuffer.B(  0 );   // signal order corresponds with J1/P1 layout
    DS1_N           << InptBuffer.B(  1 );
    DS0_N           << InptBuffer.B(  2 );
    AM( 5 )         << InptBuffer.B(  3 );
    WRITE_N         << InptBuffer.B(  4 );
    AM( 0 )         << InptBuffer.B(  5 );
    AM( 1 )         << InptBuffer.B(  6 );
    AM( 2 )         << InptBuffer.B(  7 );
    AS_N            << InptBuffer.B(  8 );
    AM( 3 )         << InptBuffer.B(  9 );
    IACK_N          << InptBuffer.B( 10 );
    IACKIN_N        << InptBuffer.B( 11 );
    AM( 4 )         << InptBuffer.B( 12 );
 
    VME_SYSRESET_N  << InptBuffer.A(  0 );   // signal order corresponds with J1/P1 layout
    VME_DS1_N       << InptBuffer.A(  1 );
    VME_DS0_N       << InptBuffer.A(  2 );
    VME_AM( 5 )     << InptBuffer.A(  3 );
    VME_WRITE_N     << InptBuffer.A(  4 );
    VME_AM( 0 )     << InptBuffer.A(  5 );
    VME_AM( 1 )     << InptBuffer.A(  6 );
    VME_AM( 2 )     << InptBuffer.A(  7 );
    VME_AS_N        << InptBuffer.A(  8 );
    VME_AM( 3 )     << InptBuffer.A(  9 );
    VME_IACK_N      << InptBuffer.A( 10 );
    VME_IACKIN_N    << InptBuffer.A( 11 );
    VME_AM( 4 )     << InptBuffer.A( 12 );
 
 
    // unused buffers: connect input to output--assumes bus hold on B port (ABTE) or both A and B ports (ABTH)
    "UNUSED_ADDR_15_01"   <<  AddrBuffer15_01.A(    15)  <<  AddrBuffer15_01.B(   15);  // one unused, formerly used for A0 (LWORD_N)
    "UNUSED_ADDR_23_16_"  <<  AddrBuffer23_16.A(15,  9)  <<  AddrBuffer23_16.B(15, 9);  // (8) is now used for A0 (LWORD_N)
    "UNUSED_ADDR_31_24_"  <<  AddrBuffer31_24.A(15,  8)  <<  AddrBuffer31_24.B(15, 8);
    "UNUSED_CTRL_15_13_"  <<  InptBuffer.A(     15, 13)  <<  InptBuffer.B(15, 13);
 
 
    //Wire-all connections
    wireall( VCC5 ); //Connect to 5V supply to upper level
    wireall( GND ); //Connect GND to upper level
 
  }
};
 
#endif