Coolquest, Inc.	Home	Products	Support	About	Contact
C++BOLD Example Design: IROD

// THIS FILE IS IN THE PUBLIC DOMAIN.
// IT IS PROVIDED AS IS WITHOUT WARRANTY OF ANY KIND, EITHER EXPRESSED OR IMPLIED, INCLUDING, BUT
// NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE.
 
#ifndef _VMEC_PLDH_
#define _VMEC_PLDH_
 
class CM_VMEC_PLD : public TModule { 
public: 
 
  //Bundles
  CB_JTAG JT;
 
  //Define ports
  port VCC;
  port GND;
  port HARDRESET_N;   // System Reset
 
  port VMEC_GEN;      // general-purpose signals from FlashPLD, e.g., used to disable VME in non-VME startup modes
 
  port GA_N;          //VME Geographical Address Bus.
  port AM;            //VME Address Modifier
  port AS_N;          //VME Address Strobe
  port DS0_N;         //VME Data Strobe 0
  port DS1_N;         //VME Data Strobe 1
  port BERR_N;        //VME Bus Error Signal (Wired but unused)
  port DTACK_N;       //VME DTACK (Data Transfer Acknowledge)
  port WRITE_N;       //VME Write (Indicates Read or Write transaction)
  port IACK_N;        //VME Interrupt Acknowledge
  port IACKIN_N;      //VME Interrupt Acknowledge In (Part of Interrupt Daisy Chain)
  port IACKOUT_N;     //VME Interrupt Acknowledge Out (Output part of Interrupt Daisy Chain)
  port LWORD_N;       //VME LWORD Signal (LSB of address bus)
  port IRQ;           //VME Interrupt Request Bus (7 Interrupts)
  port FMLD;          //Flash Memory Local Data Bus (Byte-wide)
  port A;             //VME Address Bus
  port VMEDOE_N;      //Control Signal to VME Data CPLD. Output Enable for VME Data Bus
  port VMEAOE_N;      //Control Signal to VME Data CPLD. Output Enable for VME Address Bus
  port LDOE_N;        //To VME Data CPLD. Local Data Bus Output Enable.
  port RW_N;          //Read/Write Direction signal
  port OE_N;          //Output Enable to all devices in VME Subsystem
  port VADDRCLKEN_N;  //To VME Data CPLD. Clock Enable for VME Address Bus
  port VDATACLKEN_N;  //To VME Data CPLD. Clock Enable for VME Data Bus
  port VASEL;         //To VME Data CPLD. Selects VME Address or Data Bus
  port VLDSEL;        //To VME Data CPLD. Selects between Local Data Bus (Byte-wide vs. Word-wide)
  port FREN_N;        //FIFO Read-Enable
  port FOE_N;         //FIFO Output Enable (Different from OE_N since FIFO has no Chip Enable)
  port FEF_N;         //FIFO Empty Flag
  port DPCE_N;        //Dual-Port RAM Chip Enable
  port DPBSY_N;       //Dual-Port RAM Busy Signal
  port VFL_CE_N;      //Chip Enable for FlashPLD and flash memory (via FlashPLD)
  port WE_N;          //Write-Enable to various devices in system
  port LA;            //Local Address Bus
  port INTREQ;        //Interrupt Request from Host
  port INT;           //3-bit Interrupt Bus from Host indicating which Interrupt is required
  port INTPEND;       //Status of Interrupt - to Host
  port ABUFOE_N;      //VME Address Buffers Output Enable
  port ABUFDIR;       //VME Address Buffers Direction
  port DBUFOE_N;      //VME Data Buffers Output Enable
  port DBUFDIR;       //VME Data Buffers Direction
  port IBUFOE_N;      //VME Input Buffer Output Enable
  port CLKIN;         //System Clock
  port CRCE_N;        // chip enable for CR_Flash
 
  //Instantiate parts
  CP_XC95288XL_144 Cpld;
 
  virtual void Register() {  //Register function
    //Register bundles
    reg ( JT );
 
    //Register all ports
    reg ( VCC );
    reg ( GND );
    reg ( HARDRESET_N );
 
    regb( VMEC_GEN, 1, 0 );
 
    regb( GA_N, 4, 0 );
    regb( AM, 5, 0 );
    reg ( AS_N );
    reg ( DS0_N );
    reg ( DS1_N );
    reg ( BERR_N );
    reg ( DTACK_N );
    reg ( WRITE_N );
    reg ( IACK_N );
    reg ( IACKIN_N );
    reg ( IACKOUT_N );
    reg ( LWORD_N );
    regb( IRQ, 7, 1 );
    regb( FMLD, 7, 0 );
    regb( A, 31, 1 );
    reg ( VMEDOE_N );
    reg ( VMEAOE_N );
    reg ( LDOE_N );
    reg ( RW_N );
    reg ( OE_N );
    reg ( VADDRCLKEN_N );
    reg ( VDATACLKEN_N );
    reg ( VASEL );
    reg ( VLDSEL );
    reg ( FREN_N );
    reg ( FOE_N );
    reg ( FEF_N );
    reg ( DPCE_N );
    reg ( DPBSY_N );
    reg ( VFL_CE_N );
    reg ( WE_N );
    regb( LA, 16, 2 );
    reg ( INTREQ );
    regb( INT, 2, 0 );
    reg ( INTPEND );
    reg ( ABUFOE_N );
    reg ( ABUFDIR );
    reg ( DBUFOE_N );
    reg ( DBUFDIR );
    reg ( IBUFOE_N );
    reg ( CLKIN );
    reg ( CRCE_N );
 
    //Register all instantiated parts and modules
    reg( Cpld );
  }
 
  virtual void Connect() {  //Connect function
    //Wire JTAG
    wire   ( JT, Cpld );
 
    //Connections to ports
    VMEC_GEN( 1 ) << Cpld.IO11;
    VMEC_GEN( 0 ) << Cpld.IO10;
 
    conn   ( GA_N(4), Cpld.IO142 );
    conn   ( GA_N(3), Cpld.IO140 );
    conn   ( GA_N(2), Cpld.IO139 );
    conn   ( GA_N(1), Cpld.IO138 );
    conn   ( GA_N(0), Cpld.IO137 );
    conn   ( AM(0), Cpld.IO126 );
    conn   ( AM(1), Cpld.IO125 );
    conn   ( AM(2), Cpld.IO124 );
    conn   ( AM(3), Cpld.IO121 );
    conn   ( AM(4), Cpld.IO120 );
    conn   ( AM(5), Cpld.IO119 );
    wire   ( AS_N, "IO132" );
    wire   ( DS0_N, "IO135" );
    wire   ( DS1_N, "IO136" );
    wire   ( BERR_N, "IO128" );
    wire   ( DTACK_N, "IO133" );
    wire   ( WRITE_N, "IO134" );
    wire   ( HARDRESET_N, "IO143_GSR" );
    wire   ( IACK_N, "IO131" );
    wire   ( IACKIN_N, "IO130" );
    wire   ( IACKOUT_N, "IO129" );
    wire   ( LWORD_N, "IO71" );
    conn   ( IRQ(1), Cpld.IO118 );
    conn   ( IRQ(2), Cpld.IO117 );
    conn   ( IRQ(3), Cpld.IO116 );
    conn   ( IRQ(4), Cpld.IO115 );
    conn   ( IRQ(5), Cpld.IO113 );
    conn   ( IRQ(6), Cpld.IO112 );
    conn   ( IRQ(7), Cpld.IO111 );
    conn   ( FMLD(7), Cpld.IO49 );
    conn   ( FMLD(6), Cpld.IO48 );
    conn   ( FMLD(5), Cpld.IO46 );
    conn   ( FMLD(4), Cpld.IO45 );
    conn   ( FMLD(3), Cpld.IO44 );
    conn   ( FMLD(2), Cpld.IO43 );
    conn   ( FMLD(1), Cpld.IO41 );
    conn   ( FMLD(0), Cpld.IO40 );
    conn   ( A(30), Cpld.IO110 );
    conn   ( A(29), Cpld.IO107 );
    conn   ( A(28), Cpld.IO106 );
    conn   ( A(27), Cpld.IO105 );
    conn   ( A(26), Cpld.IO104 );
    conn   ( A(25), Cpld.IO103 );
    conn   ( A(24), Cpld.IO102 );
    conn   ( A(23), Cpld.IO101 );
    conn   ( A(22), Cpld.IO100 );
    conn   ( A(21), Cpld.IO98 );
    conn   ( A(20), Cpld.IO97 );
    conn   ( A(19), Cpld.IO96 );
    conn   ( A(18), Cpld.IO95 );
    conn   ( A(17), Cpld.IO94 );
    conn   ( A(16), Cpld.IO93 );
    conn   ( A(15), Cpld.IO92 );
    conn   ( A(14), Cpld.IO91 );
    conn   ( A(13), Cpld.IO88 );
    conn   ( A(12), Cpld.IO87 );
    conn   ( A(11), Cpld.IO86 );
    conn   ( A(10), Cpld.IO85 );
    conn   ( A(9), Cpld.IO83 );
    conn   ( A(8), Cpld.IO82 );
    conn   ( A(7), Cpld.IO81 );
    conn   ( A(6), Cpld.IO80 );
    conn   ( A(5), Cpld.IO79 );
    conn   ( A(4), Cpld.IO78 );
    conn   ( A(3), Cpld.IO77 );
    conn   ( A(2), Cpld.IO76 );
    conn   ( A(1) , Cpld.IO75 );
    conn   ( A(31), Cpld.IO74 );   // strange pinout in order to preserve existing routing after bug fix
 
    "/NC"  <<      Cpld.IO12;    // formerly RETRY_N, which is no longer implemented
 
    wire   ( VMEDOE_N, "IO16" );
    wire   ( VMEAOE_N, "IO17" );
    wire   ( LDOE_N, "IO15" );
    wire   ( RW_N, "IO14" );
    wire   ( OE_N, "IO13" );
    wire   ( VADDRCLKEN_N, "IO19" );
    wire   ( VDATACLKEN_N, "IO20" );
    wire   ( VASEL, "IO21" );
    wire   ( VLDSEL, "IO22" );
    wire   ( FREN_N, "IO26" );
    wire   ( FOE_N, "IO27" );
    wire   ( FEF_N, "IO25" );
    wire   ( DPCE_N, "IO24" );
    wire   ( DPBSY_N, "IO23" );
    wire   ( VFL_CE_N, "IO28" );
    wire   ( CRCE_N,   "IO31" );
    wire   ( WE_N, "IO32_GCK2" );
    "/NC"   << Cpld.IO70;          // formerly LA(17)
    conn   ( LA(16), Cpld.IO69 );
    conn   ( LA(15), Cpld.IO68 );
    conn   ( LA(14), Cpld.IO66 );
    conn   ( LA(13), Cpld.IO64 );
    conn   ( LA(12), Cpld.IO61 );
    conn   ( LA(11), Cpld.IO60 );
    conn   ( LA(10), Cpld.IO59 );
    conn   ( LA(9), Cpld.IO58 );
    conn   ( LA(8), Cpld.IO57 );
    conn   ( LA(7), Cpld.IO56 );
    conn   ( LA(6), Cpld.IO54 );
    conn   ( LA(5), Cpld.IO53 );
    conn   ( LA(4), Cpld.IO52 );
    conn   ( LA(3), Cpld.IO51 );
    conn   ( LA(2), Cpld.IO50 );
    wire   ( INTREQ, "IO33" );
    conn   ( INT(0), Cpld.IO38_GCK3 );
    conn   ( INT(1), Cpld.IO35 );
    conn   ( INT(2), Cpld.IO34 );
    wire   ( INTPEND, "IO39" );
    wire   ( ABUFOE_N, "IO2_GTS3" );
    wire   ( ABUFDIR, "IO3_GTS4" );
    wire   ( DBUFOE_N, "IO4" );
    wire   ( DBUFDIR, "IO5_GTS1" );
    wire   ( CLKIN, "IO30_GCK1" );
 
    conn   ( "/NC", Cpld.IO6_GTS2, Cpld.IO7 );
 
    IBUFOE_N << Cpld.IO9;   // always asserted when VCC is valid, but pulled to VCC5 when VCC is < 2.5V
 
    //Wire-all connections
    wire( VCC ); //Connect VCC to upper level
    wire( VCC, "VCCIO" ); //VCCIO is 3.3V for this application
    wire( GND ); //Connect GND to upper level
 
  }
};
 
#endif