#ifndef _idt72v3690_h_
#define _idt72v3690_h_
class CP_IDT72V3690 : public TPart {
public:
port NC;
port VCC;
port GND;
port WEN_N;
port SEN_N;
port IW;
port D;
port Q;
port OE_N;
port RT_N;
port REN_N;
port RCLK;
port RM;
port EF_N_OR_N;
port PFM;
port PAE_N;
port BM;
port IP;
port BE_N;
port FS1;
port HF_N;
port FS0;
port OW;
port PAF_N;
port FF_N_IR_N;
port FWFT_SI;
port LD_N;
port MRS_N;
port PRS_N;
port WCLK;
CP_IDT72V3690() {
SetPackage( "TQFP128", 128 );
SetReferencePrefix( "U" );
}
virtual void Register() {
reg( NC );
NC.AddPin( "3" );
NC.AddPin( "5" );
reg( VCC );
VCC.AddPin( "4" );
VCC.AddPin( "11" );
VCC.AddPin( "24" );
VCC.AddPin( "35" );
VCC.AddPin( "48" );
VCC.AddPin( "61" );
VCC.AddPin( "72" );
VCC.AddPin( "73" );
VCC.AddPin( "87" );
VCC.AddPin( "100" );
VCC.AddPin( "101" );
VCC.AddPin( "111" );
VCC.AddPin( "122" );
reg( GND );
GND.AddPin( "14" );
GND.AddPin( "22" );
GND.AddPin( "29" );
GND.AddPin( "37" );
GND.AddPin( "44" );
GND.AddPin( "52" );
GND.AddPin( "59" );
GND.AddPin( "67" );
GND.AddPin( "76" );
GND.AddPin( "83" );
GND.AddPin( "84" );
GND.AddPin( "94" );
GND.AddPin( "95" );
GND.AddPin( "106" );
GND.AddPin( "116" );
GND.AddPin( "120" );
reg( WEN_N );
WEN_N.SetPin( "1" );
reg( SEN_N );
SEN_N.SetPin( "2" );
reg( IW );
IW.SetPin( "6" );
regb( D, 35, 0 );
D.AddPin( 35, "7" );
D.AddPin( 34, "8" );
D.AddPin( 33, "9" );
D.AddPin( 32, "10" );
D.AddPin( 31, "12" );
D.AddPin( 30, "13" );
D.AddPin( 29, "15" );
D.AddPin( 28, "16" );
D.AddPin( 27, "17" );
D.AddPin( 26, "18" );
D.AddPin( 25, "19" );
D.AddPin( 24, "20" );
D.AddPin( 23, "21" );
D.AddPin( 22, "23" );
D.AddPin( 21, "25" );
D.AddPin( 20, "26" );
D.AddPin( 19, "27" );
D.AddPin( 18, "28" );
D.AddPin( 17, "30" );
D.AddPin( 16, "31" );
D.AddPin( 15, "32" );
D.AddPin( 14, "33" );
D.AddPin( 13, "34" );
D.AddPin( 12, "36" );
D.AddPin( 11, "38" );
D.AddPin( 10, "39" );
D.AddPin( 9, "40" );
D.AddPin( 8, "41" );
D.AddPin( 7, "42" );
D.AddPin( 6, "43" );
D.AddPin( 5, "45" );
D.AddPin( 4, "46" );
D.AddPin( 3, "47" );
D.AddPin( 2, "49" );
D.AddPin( 1, "50" );
D.AddPin( 0, "51" );
regb( Q, 35, 0 );
Q.AddPin( 35, "99" );
Q.AddPin( 34, "98" );
Q.AddPin( 33, "97" );
Q.AddPin( 32, "96" );
Q.AddPin( 31, "93" );
Q.AddPin( 30, "92" );
Q.AddPin( 29, "91" );
Q.AddPin( 28, "90" );
Q.AddPin( 27, "89" );
Q.AddPin( 26, "88" );
Q.AddPin( 25, "86" );
Q.AddPin( 24, "85" );
Q.AddPin( 23, "82" );
Q.AddPin( 22, "81" );
Q.AddPin( 21, "80" );
Q.AddPin( 20, "79" );
Q.AddPin( 19, "78" );
Q.AddPin( 18, "77" );
Q.AddPin( 17, "75" );
Q.AddPin( 16, "74" );
Q.AddPin( 15, "71" );
Q.AddPin( 14, "70" );
Q.AddPin( 13, "69" );
Q.AddPin( 12, "68" );
Q.AddPin( 11, "66" );
Q.AddPin( 10, "65" );
Q.AddPin( 9, "64" );
Q.AddPin( 8, "63" );
Q.AddPin( 7, "62" );
Q.AddPin( 6, "60" );
Q.AddPin( 5, "58" );
Q.AddPin( 4, "57" );
Q.AddPin( 3, "56" );
Q.AddPin( 2, "55" );
Q.AddPin( 1, "54" );
Q.AddPin( 0, "53" );
reg( OE_N );
OE_N.SetPin( "102" );
reg( RT_N );
RT_N.SetPin( "103" );
reg( REN_N );
REN_N.SetPin( "104" );
reg( RCLK );
RCLK.SetPin( "105" );
reg( RM );
RM.SetPin( "107" );
reg( EF_N_OR_N );
EF_N_OR_N.SetPin( "108" );
reg( PFM );
PFM.SetPin( "109" );
reg( PAE_N );
PAE_N.SetPin( "110" );
reg( BM );
BM.SetPin( "112" );
reg( IP );
IP.SetPin( "113" );
reg( BE_N );
BE_N.SetPin( "114" );
reg( FS1 );
FS1.SetPin( "115" );
reg( HF_N );
HF_N.SetPin( "117" );
reg( FS0 );
FS0.SetPin( "118" );
reg( OW );
OW.SetPin( "119" );
reg( PAF_N );
PAF_N.SetPin( "121" );
reg( FF_N_IR_N );
FF_N_IR_N.SetPin( "123" );
reg( FWFT_SI );
FWFT_SI.SetPin( "124" );
reg( LD_N );
LD_N.SetPin( "125" );
reg( MRS_N );
MRS_N.SetPin( "126" );
reg( PRS_N );
PRS_N.SetPin( "127" );
reg( WCLK );
WCLK.SetPin( "128" );
}
};
#endif