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C++BOLD Example Parts Library

// This File Generated by:  pt_to_h.exe
// Source File:             standardheaders.pt
// Destination File:        standardheaders.h
 
#ifndef _standardheaders_h_
#define _standardheaders_h_
 
// AR_OFF -- auto registration is not needed
 
// THIS FILE IS IN THE PUBLIC DOMAIN.
// IT IS PROVIDED AS IS WITHOUT WARRANTY OF ANY KIND, EITHER EXPRESSED OR IMPLIED, INCLUDING, BUT
// NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE.
 
class CP_EMU_HEADER : public TPart {
 
public:
  port   KEY;         // missing pin:   no-connect
  port   PD;          // power-detect:  attach to VCC
  port   TMS;         
  port   TDI;         
  port   TDO;         
  port   TCK;         
  port   TRST_N;      
  port   EMU0;        
  port   EMU1;        
  port   TCK_RET;     
  port   GND;         // 4 pins
 
  CP_EMU_HEADER() {
    SetPackage( "HEADER7X2RT_100MIL", 14 );
    SetReferencePrefix( "H" );
  }
 
  virtual void Register() {
    reg(  KEY );
          KEY.SetPin( "6" );
    reg(  PD );
          PD.SetPin( "5" );
    reg(  TMS );
          TMS.SetPin( "1" );
    reg(  TDI );
          TDI.SetPin( "3" );
    reg(  TDO );
          TDO.SetPin( "7" );
    reg(  TCK );
          TCK.SetPin( "11" );
    reg(  TRST_N );
          TRST_N.SetPin( "2" );
    reg(  EMU0 );
          EMU0.SetPin( "13" );
    reg(  EMU1 );
          EMU1.SetPin( "14" );
    reg(  TCK_RET );
          TCK_RET.SetPin( "9" );
    reg(  GND );
          GND.AddPin( "4" );
          GND.AddPin( "8" );
          GND.AddPin( "10" );
          GND.AddPin( "12" );
  }
};
 
class CP_JTAG_HEADER : public TPart {
 
public:
  port   TCK;          // output from POD to   motherboard
  port   TMS;          // output from POD to   motherboard
  port   TDI;          // output from POD to   motherboard
  port   TDO;          // input to    POD from motherboard
  port   TRST_N;       // not normally used
  port   BYPASS_N;     // not normally used
  port   P_ENA;        // not normally used
  port   VCC;          // 3.3V typ from motherboard to POD
  port   GND;          // 2 pins
 
  CP_JTAG_HEADER() {
    SetPackage( "HEADER5X2RT_100MIL", 10 );
    SetReferencePrefix( "H" );
  }
 
  virtual void Register() {
    reg(  TCK );
          TCK.SetPin( "1" );
    reg(  TMS );
          TMS.SetPin( "3" );
    reg(  TDI );
          TDI.SetPin( "5" );
    reg(  TDO );
          TDO.SetPin( "7" );
    reg(  TRST_N );
          TRST_N.SetPin( "9" );
    reg(  BYPASS_N );
          BYPASS_N.SetPin( "2" );
    reg(  P_ENA );
          P_ENA.SetPin( "10" );
    reg(  VCC );
          VCC.SetPin( "6" );
    reg(  GND );
          GND.AddPin( "4" );
          GND.AddPin( "8" );
  }
};
 
class CP_INTLK_HEADER : public TPart {
 
public:
  port   IN;          // AR_BUS(1,0)
  port   OUT;         // AR_BUS(1,0)
  port   NC;          // 2 pins
  port   GND_JMP;     // 4 pins  // connect to GND via jumper --> cable ground can be isolated
 
  CP_INTLK_HEADER() {
    SetPackage( "HEADER5X2RT_100MIL", 10 );
    SetReferencePrefix( "H" );
  }
 
  virtual void Register() {
    regb( IN, 1, 0 );
          IN.AddPin( 1, "7" );
          IN.AddPin( 0, "3" );
    regb( OUT, 1, 0 );
          OUT.AddPin( 1, "4" );
          OUT.AddPin( 0, "9" );
    reg(  NC );
          NC.AddPin( "1" );
          NC.AddPin( "5" );
    reg(  GND_JMP );
          GND_JMP.AddPin( "2" );
          GND_JMP.AddPin( "6" );
          GND_JMP.AddPin( "8" );
          GND_JMP.AddPin( "10" );
  }
};
 
class CP_TXIO_HEADER : public TPart {     // for CTM
 
public:
  port   IN;        // AR_BUS(1,0)  // two inputs to all Tx FPGA's
  port   OUT0_;     // AR_BUS(1,0)  // two outputs from each Tx FPGA
  port   OUT1_;     // AR_BUS(1,0)
  port   OUT2_;     // AR_BUS(1,0)
  port   GND;       // 8 pins
 
  CP_TXIO_HEADER() {
    SetPackage( "HEADER8X2RT_100MIL", 16 );
    SetReferencePrefix( "H" );
  }
 
  virtual void Register() {
    regb( IN, 1, 0 );
          IN.AddPin( 1, "3" );
          IN.AddPin( 0, "1" );
    regb( OUT0_, 1, 0 );
          OUT0_.AddPin( 1, "7" );
          OUT0_.AddPin( 0, "5" );
    regb( OUT1_, 1, 0 );
          OUT1_.AddPin( 1, "11" );
          OUT1_.AddPin( 0, "9" );
    regb( OUT2_, 1, 0 );
          OUT2_.AddPin( 1, "15" );
          OUT2_.AddPin( 0, "13" );
    reg(  GND );
          GND.AddPin( "2" );
          GND.AddPin( "4" );
          GND.AddPin( "6" );
          GND.AddPin( "8" );
          GND.AddPin( "10" );
          GND.AddPin( "12" );
          GND.AddPin( "14" );
          GND.AddPin( "16" );
  }
};
 
class CP_TTC_HEADER : public TPart {     // for ROD
 
public:
  port   RCLKIP;     // clock inputs
  port   RCLKIN;     
  port   TCLKIP;     
  port   TCLKIN;     
  port   TTC0P;      // general-purpose inputs to TTC FPGA, e.g., L1 trigger
  port   TTC0N;      
  port   TTC1P;      
  port   TTC1N;      
  port   GND;        // 8 pins
 
  CP_TTC_HEADER() {
    SetPackage( "HEADER8X2RT_100MIL", 16 );
    SetReferencePrefix( "H" );
  }
 
  virtual void Register() {
    reg(  RCLKIP );
          RCLKIP.SetPin( "3" );
    reg(  RCLKIN );
          RCLKIN.SetPin( "4" );
    reg(  TCLKIP );
          TCLKIP.SetPin( "7" );
    reg(  TCLKIN );
          TCLKIN.SetPin( "8" );
    reg(  TTC0P );
          TTC0P.SetPin( "11" );
    reg(  TTC0N );
          TTC0N.SetPin( "12" );
    reg(  TTC1P );
          TTC1P.SetPin( "13" );
    reg(  TTC1N );
          TTC1N.SetPin( "14" );
    reg(  GND );
          GND.AddPin( "1" );
          GND.AddPin( "2" );
          GND.AddPin( "5" );
          GND.AddPin( "6" );
          GND.AddPin( "9" );
          GND.AddPin( "10" );
          GND.AddPin( "15" );
          GND.AddPin( "16" );
  }
};
 
 
#endif