#ifndef _xc9572xl_h_
#define _xc9572xl_h_
class CP_XC9572XL : public TPart {
public:
port VCCINT;
port VCC;
port GND;
port TCK;
port TDI;
port TDO;
port TMS;
port IO1;
port IO2_GTS2;
port IO4;
port IO5_GTS1;
port IO6;
port IO7;
port IO8;
port IO9;
port IO10;
port IO11;
port IO12;
port IO13;
port IO15_GCK1;
port IO16_GCK2;
port IO17_GCK3;
port IO18;
port IO19;
port IO20;
port IO22;
port IO23;
port IO24;
port IO25;
port IO27;
port IO31;
port IO32;
port IO33;
port IO34;
port IO35;
port IO36;
port IO38;
port IO39;
port IO40;
port IO42;
port IO43;
port IO44;
port IO45;
port IO46;
port IO47;
port IO48;
port IO49;
port IO50;
port IO51;
port IO52;
port IO56;
port IO57;
port IO58;
port IO59;
port IO60;
port IO61;
port IO62;
port IO63;
port IO64_GSR;
CP_XC9572XL() {
SetPackage( "VQFP64", 64 );
SetReferencePrefix( "U" );
}
virtual void Register() {
reg( VCCINT );
VCCINT.AddPin( "3" );
VCCINT.AddPin( "37" );
reg( VCC );
VCC.AddPin( "26" );
VCC.AddPin( "55" );
reg( GND );
GND.AddPin( "14" );
GND.AddPin( "21" );
GND.AddPin( "41" );
GND.AddPin( "54" );
reg( TCK );
TCK.SetPin( "30" );
reg( TDI );
TDI.SetPin( "28" );
reg( TDO );
TDO.SetPin( "53" );
reg( TMS );
TMS.SetPin( "29" );
reg( IO1 );
IO1.SetPin( "1" );
reg( IO2_GTS2 );
IO2_GTS2.SetPin( "2" );
reg( IO4 );
IO4.SetPin( "4" );
reg( IO5_GTS1 );
IO5_GTS1.SetPin( "5" );
reg( IO6 );
IO6.SetPin( "6" );
reg( IO7 );
IO7.SetPin( "7" );
reg( IO8 );
IO8.SetPin( "8" );
reg( IO9 );
IO9.SetPin( "9" );
reg( IO10 );
IO10.SetPin( "10" );
reg( IO11 );
IO11.SetPin( "11" );
reg( IO12 );
IO12.SetPin( "12" );
reg( IO13 );
IO13.SetPin( "13" );
reg( IO15_GCK1 );
IO15_GCK1.SetPin( "15" );
reg( IO16_GCK2 );
IO16_GCK2.SetPin( "16" );
reg( IO17_GCK3 );
IO17_GCK3.SetPin( "17" );
reg( IO18 );
IO18.SetPin( "18" );
reg( IO19 );
IO19.SetPin( "19" );
reg( IO20 );
IO20.SetPin( "20" );
reg( IO22 );
IO22.SetPin( "22" );
reg( IO23 );
IO23.SetPin( "23" );
reg( IO24 );
IO24.SetPin( "24" );
reg( IO25 );
IO25.SetPin( "25" );
reg( IO27 );
IO27.SetPin( "27" );
reg( IO31 );
IO31.SetPin( "31" );
reg( IO32 );
IO32.SetPin( "32" );
reg( IO33 );
IO33.SetPin( "33" );
reg( IO34 );
IO34.SetPin( "34" );
reg( IO35 );
IO35.SetPin( "35" );
reg( IO36 );
IO36.SetPin( "36" );
reg( IO38 );
IO38.SetPin( "38" );
reg( IO39 );
IO39.SetPin( "39" );
reg( IO40 );
IO40.SetPin( "40" );
reg( IO42 );
IO42.SetPin( "42" );
reg( IO43 );
IO43.SetPin( "43" );
reg( IO44 );
IO44.SetPin( "44" );
reg( IO45 );
IO45.SetPin( "45" );
reg( IO46 );
IO46.SetPin( "46" );
reg( IO47 );
IO47.SetPin( "47" );
reg( IO48 );
IO48.SetPin( "48" );
reg( IO49 );
IO49.SetPin( "49" );
reg( IO50 );
IO50.SetPin( "50" );
reg( IO51 );
IO51.SetPin( "51" );
reg( IO52 );
IO52.SetPin( "52" );
reg( IO56 );
IO56.SetPin( "56" );
reg( IO57 );
IO57.SetPin( "57" );
reg( IO58 );
IO58.SetPin( "58" );
reg( IO59 );
IO59.SetPin( "59" );
reg( IO60 );
IO60.SetPin( "60" );
reg( IO61 );
IO61.SetPin( "61" );
reg( IO62 );
IO62.SetPin( "62" );
reg( IO63 );
IO63.SetPin( "63" );
reg( IO64_GSR );
IO64_GSR.SetPin( "64" );
}
};
#endif