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C++BOLD Example Design: IROD

// THIS FILE IS IN THE PUBLIC DOMAIN.
// IT IS PROVIDED AS IS WITHOUT WARRANTY OF ANY KIND, EITHER EXPRESSED OR IMPLIED, INCLUDING, BUT
// NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE.
 
#ifndef _DataExchangeH_
#define _DataExchangeH_
 
#include "dxf_fpga.h"         // front and back FPGA's
#include "dxb_fpga.h"
#include "std_fifo.h"
 
// All necessary decoupling capacitors are already included.
 
// The Data Exchange subsystem builds packets and routes them between the following:
//   HPU
//   DPU's
//   generic DX backplane pins (DG)
 
 
 
// CB_Back_DX: interface between Backplane and DataExchange
class CB_Back_DX : public TBundle {
public:
  port DG;           // DX generic connections to backplane
 
  virtual void Register() {
    regb( DG, 56, 0 );          //  !! check count
  }
};
 
 
 
 
// CB_Half_DX: interface between HalfROD and DataExchange
class CB_Half_DX : public TBundle {
public:
  port DXD;    // data bus between a DXF FPGA and its corresponding Half-ROD
  port DXC;    // control bus, e.g., DAV, END, AL_END, BROADCAST, DEST_AF, four MSB's have pullups for OR-tie
 
  virtual void Register() {
    regb( DXD, 31, 0 );
    regb( DXC,  9, 0 );
  }
};
 
 
// CB_Host_DX: interface between Host and DataExchange
class CB_Host_DX : public TBundle {
public:
                   // Host asynchronous EMIF connections (via FPGA, transceiver, PLD, etc.)
  port BDH;        // buffered data (to DX FPGA's)
  port BDF;        // buffered data (to Host FIFO)
  port A;          // address
  port DXF_STB_N;  // one strobe per DXF FPGA
  port DXB_STB_N;  // one strobe for the DXB FPGA
  port WR_N;       // one read/write* signal to all FPGA's
 
  port HFIFO_OE_N;     // Host FIFO control signals
  port HFIFO_REN_N;
  port HFIFO_RD_CLK;
  port HFIFO_EF_N;     // to Host PLD
  port HFIFO_PAE_N;    // to Host PLD
 
  port DXF_HG;         // generic bus, Host <--> DXF FPGA's, pullups are provided for OR-tie
  port DXB_HG;         // generic bus, Host <--> DXB FPGA
 
  virtual void Register() {
    regb(   BDH, 31, 0 );
    regb(   BDF, 31, 0 );
    regb(     A,  3, 0 );
    regb( DXF_STB_N, 1, 0 );
    reg(  DXB_STB_N );
    reg(  WR_N );
 
    reg(  HFIFO_OE_N  );
    reg(  HFIFO_REN_N  );
    reg(  HFIFO_RD_CLK );
    reg(  HFIFO_EF_N   );
    reg(  HFIFO_PAE_N  );
 
    regb( DXF_HG, 3, 0 );
    regb( DXB_HG, 3, 0 );
  }
};
 
 
 
 
class CM_DataExchange : public TModule {    // Data Exchange Subsystem
public:
// ***** member bundles ***** //
  CB_Back_DX  BK;    // interface to Backplane
  CB_DX_CG    CG;    // interface to ClockGeneration
  CB_Half_DX  A;     // interface to Half A
  CB_Half_DX  B;     // interface to Half B
  CB_Host_DX  H;     // interface to Host
  CB_DX_JT    JT;    // interface to JTAG
 
 
// ***** member ports ***** //
  port MB_VCC;      // 3.3V
  port MB_VB;       // 2.5V for FPGA internal
  port GND;
 
 
// ***** member modules and parts ***** //
  CM_DXF_FPGA  DXF_FPGA_A;   // one DX front-end FPGA for each HalfROD
  CM_DXF_FPGA  DXF_FPGA_B;
  CM_DXB_FPGA  DXB_FPGA;
  CM_STD_FIFO  HostFIFO;
 
  CP_R360     PullupDXF_HG[ 4 ];  // pullups for OR-tie
  CP_R360     PullupDXC_A9;
  CP_R360     PullupDXC_A8;
  CP_R360     PullupDXC_A7;
  CP_R360     PullupDXC_A6;
  CP_R360     PullupDXC_B9;
  CP_R360     PullupDXC_B8;
  CP_R360     PullupDXC_B7;
  CP_R360     PullupDXC_B6;
 
  CP_R4_7K    PullupMRS;          // pullups in case no FPGA is driving these FIFO inputs
  CP_R4_7K    PullupWEN;
  CP_R4_7K    PullupLD;
 
 
  port DXF_HG;         // generic bus, Host <--> DXF FPGA's, pullups are provided for OR-tie
 
  virtual void Register() {
// bundles
    reg( BK );
    reg( CG );
    reg( A );
    reg( B );
    reg( H );
    reg( JT );
 
// ports
    reg( MB_VCC );
    reg( MB_VB  );
    reg( GND );
 
// parts and modules
    reg(  DXF_FPGA_A );
    reg(  DXF_FPGA_B );
    reg(  DXB_FPGA   );
    reg(  HostFIFO   );
 
    rega( PullupDXF_HG, 4 );
    reg(  PullupDXC_A9 );
    reg(  PullupDXC_A8 );
    reg(  PullupDXC_A7 );
    reg(  PullupDXC_A6 );
    reg(  PullupDXC_B9 );
    reg(  PullupDXC_B8 );
    reg(  PullupDXC_B7 );
    reg(  PullupDXC_B6 );
 
    reg(  PullupMRS );
    reg(  PullupWEN );
    reg(  PullupLD );
  }
 
  virtual void Connect() {
    wireall( MB_VCC, "VCC" );
    wireall( MB_VB,  "VB"  );
    wireall( GND );
 
    JT.DXB_FPGA    <<    DXB_FPGA.JTAG_CONF;
    JT.DXF_FPGA_A  <<  DXF_FPGA_A.JTAG_CONF;
    JT.DXF_FPGA_B  <<  DXF_FPGA_B.JTAG_CONF;
 
// ID straps
    GND     <<  DXF_FPGA_A.STRAP;
    MB_VCC  <<  DXF_FPGA_B.STRAP;
 
// connections between DXF FPGA's
    wire2( "INTER_DXF" );
 
// connections between all FPGA's (and some to FIFO)
    "INTER_DX"          <<  DXF_FPGA_A.INTER_DX( 33, 0 );    // 34 LSB's are a bus
    "INTER_DX"          <<  DXF_FPGA_B.INTER_DX( 33, 0 );
    "INTER_DX"          <<  DXB_FPGA.INTER_DX;
    HostFIFO.D( 31, 0 ) <<  DXB_FPGA.INTER_DX( 31, 0);       // 32 LSB's to FIFO
 
    "INTER_DX_A"        <<  DXF_FPGA_A.INTER_DX( 35, 34 );   // 2 MSB's are pt-to-pt
    "INTER_DX_A"        <<  DXB_FPGA.INTER_DX_A;
    "INTER_DX_B"        <<  DXF_FPGA_B.INTER_DX( 35, 34 );
    "INTER_DX_B"        <<  DXB_FPGA.INTER_DX_B;
 
 
// connections to other subsystems via CB_... interfaces
    // front FPGA's
    int k = 0;
    CG.DX_CLK(    0 )  <<  DXF_FPGA_A.DX_CLK;   // one DX_CLK shared by both DXF_FPGA's
    CG.DXINT_CLK( k )  <<  DXF_FPGA_A.DXINT_CLK;
    CG.DCLK(      k )  <<  DXF_FPGA_A.DCLK;
    wire(  A,              DXF_FPGA_A );       // side A
    wire(  H,              DXF_FPGA_A );
    H.BDH              <<  DXF_FPGA_A.D;       // additional for H
    H.DXF_STB_N(  k )  <<  DXF_FPGA_A.STB_N;   // additional for H
 
    k ++;
    CG.DX_CLK(    0 )  <<  DXF_FPGA_B.DX_CLK;
    CG.DXINT_CLK( k )  <<  DXF_FPGA_B.DXINT_CLK;
    CG.DCLK(      k )  <<  DXF_FPGA_B.DCLK;
    wire(  B,              DXF_FPGA_B );       // side B
    wire(  H,              DXF_FPGA_B );
    H.BDH              <<  DXF_FPGA_B.D;       // additional for H
    H.DXF_STB_N(  k )  <<  DXF_FPGA_B.STB_N;   // additional for H
 
 
    for ( int i = 0; i < 4; ++ i ) {
       H.DXF_HG( i )  ^ PullupDXF_HG[ i ] ^ MB_VCC;     // pullups for OR-tie of generic bus from DXF FPGA's to Host
    }
    DXF_FPGA_A.DXC(  9 )  ^  PullupDXC_A9   ^  MB_VCC;  // pullups for OR-tie, 4 MSB's of DXC bus to halves
    DXF_FPGA_A.DXC(  8 )  ^  PullupDXC_A8   ^  MB_VCC;
    DXF_FPGA_A.DXC(  7 )  ^  PullupDXC_A7   ^  MB_VCC;
    DXF_FPGA_A.DXC(  6 )  ^  PullupDXC_A6   ^  MB_VCC;
 
    DXF_FPGA_B.DXC(  9 )  ^  PullupDXC_B9   ^  MB_VCC;
    DXF_FPGA_B.DXC(  8 )  ^  PullupDXC_B8   ^  MB_VCC;
    DXF_FPGA_B.DXC(  7 )  ^  PullupDXC_B7   ^  MB_VCC;
    DXF_FPGA_B.DXC(  6 )  ^  PullupDXC_B6   ^  MB_VCC;
 
    // back FPGA
    k++;
    CG.DX_CLK(    1 )  <<  DXB_FPGA.DX_CLK;
    CG.DXINT_CLK( k )  <<  DXB_FPGA.DXINT_CLK;
    CG.DCLK(      k )  <<  DXB_FPGA.DCLK;
    wire(  H,              DXB_FPGA );
    H.BDH              <<  DXB_FPGA.D;         // additional for H
    H.DXB_STB_N        <<  DXB_FPGA.STB_N;     // additional for H
    BK.DG              <<  DXB_FPGA.DG;        // generics to backplane
 
    // FIFO
    k++;
    CG.DXINT_CLK( k )  <<  HostFIFO.WR_CLK;
 
    H.BDF              <<  HostFIFO.Q;
    H.HFIFO_OE_N       <<  HostFIFO.OE_N;
    H.HFIFO_REN_N      <<  HostFIFO.REN_N;
    H.HFIFO_RD_CLK     <<  HostFIFO.RD_CLK;
    H.HFIFO_EF_N       <<  HostFIFO.EF_N;
    H.HFIFO_PAE_N      <<  HostFIFO.PAE_N;
 
  // FIFO control signals from DXF_FPGA's
    "HFIFO_MRS_N"  <<      HostFIFO.MRS_N
                   << DXF_FPGA_A.HF_MRS_N
                   << DXF_FPGA_B.HF_MRS_N
                    ^         PullupMRS    ^ MB_VCC;        // pullup
 
    "HFIFO_WEN_N"  <<      HostFIFO.WEN_N
                   << DXF_FPGA_A.HF_WEN_N
                   << DXF_FPGA_B.HF_WEN_N
                    ^         PullupWEN    ^ MB_VCC;        // pullup
 
    "HFIFO_LD_N"   <<      HostFIFO.LD_N
                   << DXF_FPGA_A.HF_LD_N
                   << DXF_FPGA_B.HF_LD_N
                    ^         PullupLD     ^ MB_VCC;        // pullup
 
  // FIFO almost full flag to DXF_FPGA's
    "HFIFO_PAF_N"  <<      HostFIFO.PAF_N
                   << DXF_FPGA_A.HF_PAF_N
                   << DXF_FPGA_B.HF_PAF_N;
 
  }
};
 
#endif