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C++BOLD Example Design: IROD

// THIS FILE IS IN THE PUBLIC DOMAIN.
// IT IS PROVIDED AS IS WITHOUT WARRANTY OF ANY KIND, EITHER EXPRESSED OR IMPLIED, INCLUDING, BUT
// NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE.
 
#ifndef _HostPLDH_
#define _HostPLDH_
 
#include "xc95144xl_100.h"
 
// Wrapper for Host CPLD
class CM_HostPLD : public TModule {
public:
 
// ***** member bundles ***** //
  CB_JTAG JT;
 
// ***** member ports ***** //
  port VCC;  //Power and ground
  port GND;
 
  port BDF_OE_N;  //XCVR Output Enables
  port BDG_OE_N;
  port BDH_OE_N;
 
  port BDF_DIR;  //XCVR Direction
  port BDG_DIR;
  port BDH_DIR;
 
  port ARE_N;  //Asynchronous Signals from DSP
  port AWE_N;
  port AOE_N;
  port ARDY;
 
  port BA;  //Address + Data Bus from HPU
  port BDH;
 
  port CE0_N;  //Chip Enables from DSP (all but CE3, which is used for the DRAM on the HPU)
  port CE1_N;
  port CE2_N;
                  // FlashPld, flash memory control signals from host
  port HFL_A;     // address (selects between FlashPld internal registers and flash memory
  port HFL_OE_N;  // read strobe
  port HFL_WE_N;  // write strobe
  port HFL_SPARE; // not currently used
 
  port DP_OE_N;   //Dual-Port RAM Control Signals
  port DP_CE_N;
  port DP_WE_N;
  port DP_INT_N;
  port DP_BUSY_N;
 
  port HINT;         //Host->VME Interrupts
  port HINTREQ;
  port HINTPEND;
 
  port VFIFO_WEN_N;  //VME Fifo Control Signals
  port VFIFO_WR_CLK;
  port VFIFO_PAF_N;
 
  port HFIFO_RD_CLK;  //Host Fifo Control Signals
  port HFIFO_REN_N;
  port HFIFO_EF_N;
  port HFIFO_OE_N;
  port HFIFO_PAE_N;
 
                  // Read/Write + Data Strobes for TTC + BPI + CG + DX FPGAs and CPLDs
  port WR_N;      // read/write (not a strobe)
  port DX_WR_N;   // for reduced loading on WR_N, logically the same as WR_N, to data exchange subsystem
  port TTC_DS_N;
  port BPI_DS_N;  //6 Data Strobes, 1 per BPI FPGA
  port CG_DS_N;
  port DXFA_DS_N; //Front FPGAs
  port DXFB_DS_N;
  port DXB_DS_N;  //Back FPGA
 
  port ASEL;         // selects for power measurement analog mux
 
  port SN_DATA;      // serial number chip data pin
 
  port SOFTRESET_N;
 
// ***** member parts and modules ***** //
  CP_XC95144XL_100 Cpld;
 
 
  virtual void Register() {
// bundles
    reg ( JT );
 
// ports
    reg ( VCC );
    reg ( GND );
 
    reg ( BDF_OE_N );
    reg ( BDG_OE_N );
    reg ( BDH_OE_N );
 
    reg ( BDF_DIR );
    reg ( BDG_DIR );
    reg ( BDH_DIR );
 
    reg ( ARE_N );
    reg ( AWE_N );
    reg ( AOE_N );
    reg ( ARDY );
 
    regb( BA, 21, 14 );
    regb( BDH, 7,  0 );
 
    reg ( CE0_N );
    reg ( CE1_N );
    reg ( CE2_N );
 
    reg ( HFL_A     );
    reg ( HFL_WE_N  );
    reg ( HFL_OE_N  );
    reg ( HFL_SPARE );
 
    reg ( DP_OE_N );
    reg ( DP_CE_N );
    reg ( DP_WE_N );
    reg ( DP_INT_N );
    reg ( DP_BUSY_N );
 
    regb( HINT, 2, 0 );
    reg ( HINTREQ );
    reg ( HINTPEND );
 
    reg ( VFIFO_WEN_N );
    reg ( VFIFO_WR_CLK );
    reg ( VFIFO_PAF_N );
 
    reg ( HFIFO_RD_CLK );
    reg ( HFIFO_REN_N );
    reg ( HFIFO_EF_N );
    reg ( HFIFO_OE_N );
    reg ( HFIFO_PAE_N );
 
    reg ( WR_N );
    reg ( DX_WR_N );
    reg ( TTC_DS_N );
    regb( BPI_DS_N, 5, 0 );  //6 Data Strobes, 1 per BPI FPGA
    reg ( CG_DS_N );
    reg ( DXFA_DS_N );
    reg ( DXFB_DS_N );
    reg ( DXB_DS_N );
 
    regb( ASEL, 3, 0 );
    reg ( SN_DATA    );
    reg ( SOFTRESET_N );
 
// parts and modules
    reg ( Cpld );
  }
 
  virtual void Connect() {
 
    wireall( VCC );
    wireall( GND );
 
    VCC << Cpld.VCCIO;  //VCC and VCCIO on the PLD are the same
 
    //JTAG Signals
    wire ( JT, Cpld );
 
    //!! All Pins temporarily assigned by approximate location of layout estimation !!
    //!! Check before laying out !!
 
    "/NC"  << Cpld.IO1_GTS3;
    "/NC"  << Cpld.IO2_GTS4;
    "/NC"  << Cpld.IO3_GTS1;
    "/NC"  << Cpld.IO4_GTS2;
 
    //EMIF Busses
    BA(14) << Cpld.IO6;
    BA(15) << Cpld.IO7;
    BA(16) << Cpld.IO8;
    BA(17) << Cpld.IO9;
    BA(18) << Cpld.IO10;
    BA(19) << Cpld.IO11;
    BA(20) << Cpld.IO12;
    BA(21) << Cpld.IO13;
 
    BDH(0) << Cpld.IO14;
    BDH(1) << Cpld.IO15;
    BDH(2) << Cpld.IO16;
    BDH(3) << Cpld.IO17;
    BDH(4) << Cpld.IO18;
    BDH(5) << Cpld.IO19;
    BDH(6) << Cpld.IO20;
    BDH(7) << Cpld.IO24;
 
    //Chip Enables
    CE0_N  << Cpld.IO97;
    CE1_N  << Cpld.IO96;
    CE2_N  << Cpld.IO95;
 
    //XCVR Output Enables and Directions
    BDF_OE_N << Cpld.IO94;
    BDG_OE_N << Cpld.IO93;
    BDH_OE_N << Cpld.IO92;
 
    BDF_DIR << Cpld.IO91;
    BDG_DIR << Cpld.IO90;
    BDH_DIR << Cpld.IO89;
 
    //VME FIFO Control
    VFIFO_WEN_N  << Cpld.IO87;
    VFIFO_WR_CLK << Cpld.IO86;  // !! this has series terminators in CM_Host
    VFIFO_PAF_N  << Cpld.IO85;
 
    //Host FIFO Control
    HFIFO_RD_CLK << Cpld.IO82;  // !! this has series terminators in CM_Host
    HFIFO_REN_N  << Cpld.IO81;
    HFIFO_EF_N   << Cpld.IO80;
    HFIFO_OE_N   << Cpld.IO79;
    HFIFO_PAE_N  << Cpld.IO78;
 
    //Dual-Port RAM Control
    DP_OE_N   << Cpld.IO77;
    DP_CE_N   << Cpld.IO76;
    DP_WE_N   << Cpld.IO74;  // !! this has series terminators in CM_Host
    DP_INT_N  << Cpld.IO73;
    DP_BUSY_N << Cpld.IO72;
 
    //Host->VME Interrupts
    HINT(2)  << Cpld.IO71;
    HINT(1)  << Cpld.IO70;
    HINT(0)  << Cpld.IO68;
    HINTREQ  << Cpld.IO67;
    HINTPEND << Cpld.IO66;
 
    HFL_SPARE << Cpld.IO65;
 
    //Flash Memory Control
    HFL_A     << Cpld.IO25;
    HFL_WE_N  << Cpld.IO28;
    HFL_OE_N  << Cpld.IO29;
 
    //Read/Write Direction
    DX_WR_N     << Cpld.IO54;      // fan out WR_N to two pins, one dedicated to Data Exchange subsystem (3 loads)
    WR_N        << Cpld.IO30;      // all others (8 loads)
 
    // Strobes
    BPI_DS_N(0) << Cpld.IO32;  // !! these have series terminators in CM_Host
    BPI_DS_N(1) << Cpld.IO33;
    BPI_DS_N(2) << Cpld.IO34;
    BPI_DS_N(3) << Cpld.IO35;
    BPI_DS_N(4) << Cpld.IO36;
    BPI_DS_N(5) << Cpld.IO37;
    TTC_DS_N    << Cpld.IO39;
    CG_DS_N     << Cpld.IO40;
    DXFA_DS_N   << Cpld.IO41;
    DXFB_DS_N   << Cpld.IO42;
    DXB_DS_N    << Cpld.IO43;
 
    ASEL( 0 )   <<  Cpld.IO46;   // selects for power measurement mux, here because few spare pins elsewhere
    ASEL( 1 )   <<  Cpld.IO49;
    ASEL( 2 )   <<  Cpld.IO50;
    ASEL( 3 )   <<  Cpld.IO52;
 
    SN_DATA     <<  Cpld.IO53;
 
    SOFTRESET_N << Cpld.IO99_GSR;
 
    "/NC"  <<  Cpld.IO22_GCK1;
    "/NC"  <<  Cpld.IO23_GCK2;
 
    // Asynchronous EMIF Signals
    AWE_N  <<  Cpld.IO27_GCK3;
    ARE_N  <<  Cpld.IO55;
    AOE_N  <<  Cpld.IO56;
    ARDY   <<  Cpld.IO58;
 
    "/NC"  <<  Cpld.IO59;
    "/NC"  <<  Cpld.IO60;
    "/NC"  <<  Cpld.IO61;
    "/NC"  <<  Cpld.IO63;
    "/NC"  <<  Cpld.IO64;
  }
};
 
#endif