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C++BOLD Example Design: IROD

// THIS FILE IS IN THE PUBLIC DOMAIN.
// IT IS PROVIDED AS IS WITHOUT WARRANTY OF ANY KIND, EITHER EXPRESSED OR IMPLIED, INCLUDING, BUT
// NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE.
 
#ifndef _GpuH_
#define _GpuH_
 
#include "cb_base.h"
#include "cb_shorthand.h"
 
#include "interconnect.h"
#include "dpu_control.h"
#include "data_exchange.h"
 
#include "gpuconn.h"
#include "sn74cbtlv1g125.h"
#include "standardheaders.h"         // for HPU's FPGA JTAG header
 
// GPU:    Generic Processing Unit (instantiated only via descendants DPU and HPU)
//   HPU:  Host Processing Unit
//   DPU:  Data Processing Unit
 
// These modules provide all required decoupling.
 
// Clock names as they appear on GPU schematics (- means signal does not leave the GPU)
//           XB FPGA   EMIF FPGA
//           -------   ---------
//  GCK0:    RCLK      EGCK0
//  GCK1:    SCLK      EGCK1
//  GCK2:    XCLKIN    CLKOUT2 -
//  GCK3:    MUXCLK -  XCLKIN
 
 
class CB_GPU_Clocks : public TBundle {
public:
                 // conn              XB FPGA  EMIF FPGA    CPU
                 // ---------------   -------  ---------    ---------
  port CLKIN;    // .CLKIN             nc       nc           CLKIN
  port RCLK;     // .RCLK, .EGCK0      GCK0     GCK0         nc
  port SCLK;     // .SCLK              GCK1     nc           nc
  port DC_CLK;   // .XCLKIN            GCK2     GCK2         XCLKIN
  port DX_CLK;   // .EGCK1             nc       GCK1         nc
 
  virtual void Register() {
    reg( CLKIN  );
    reg( RCLK   );
    reg( SCLK   );
    reg( DC_CLK );
    reg( DX_CLK );
  }
};
 
 
class CM_GPU : public TModule {
protected:
  CM_GPU(){};                    // only descendants of this class can be instantiated by user
public:
// ***** member bundles ***** //
  CB_GPU_Clocks Clocks;
  CB_Emulator   Emulator;
 
// ***** member ports ***** //
  port DSP_VCC;      // 3.3V
  port DSP_VB;       // 2.5V for FPGA internal
  port DSP_VA;       // VCORE for DSP
  port GND;
 
 
// ***** member modules and parts ***** //
  CP_GPU_CONN           Conn;              // DSP module connector
  CP_SN74CBTLV1G125DBV  SwitchEMU;         // FET switch connects emulator TDI to TDO when module is not installed
  CP_R4_7K              PulldownPRESENT;   // pulldown for Switch's OE_N
 
  CP_R4_7K              PullupFINIT_N;
  CP_R4_7K              PullupEFINIT_N;
  CP_R360               PullupVREF;        // VREF for XB FPGA = DSP_VCC/2
  CP_R360               PulldownVREF;
 
 
  // decoupling
  enum { vc_cdc_count =  4,
         vb_cdc_count =  4,
         va_cdc_count =  4,
         vc_tdc_count =  1,
         vb_tdc_count =  1,
         va_tdc_count =  1 };
  CP_CDC_POS  VC_CDC[ vc_cdc_count ];    // ceramic decoupling
  CP_CDC_POS  VB_CDC[ vb_cdc_count ];
  CP_CDC_POS  VA_CDC[ va_cdc_count ];
  CP_TDC_POS  VC_TDC[ vc_tdc_count ];    // tantalum decoupling
  CP_TDC_POS  VB_TDC[ vb_tdc_count ];
  CP_TDC_POS  VA_TDC[ va_tdc_count ];
 
 
 
  virtual void Register() {
// bundles
    reg( Clocks );
    reg( Emulator );
 
// ports
    reg( DSP_VCC );
    reg( DSP_VB );
    reg( DSP_VA );
    reg( GND );
 
// parts and modules
    reg( Conn );
    reg( SwitchEMU );
    reg( PulldownPRESENT );
    reg( PullupFINIT_N );
    reg( PullupEFINIT_N );
    reg( PullupVREF );
    reg( PulldownVREF );
 
    rega( VC_CDC, vc_cdc_count );
    rega( VB_CDC, vb_cdc_count );
    rega( VA_CDC, va_cdc_count );
    rega( VC_TDC, vc_tdc_count );
    rega( VB_TDC, vb_tdc_count );
    rega( VA_TDC, va_tdc_count );
  }
 
  virtual void Connect() {
// bundles
    wire( Emulator, Conn );   // wire up all identically-named ports
 
    Clocks.CLKIN    <<  Conn.CLKIN;
    Clocks.RCLK     <<  Conn.RCLK    <<  Conn.EGCK0;
    Clocks.SCLK     <<  Conn.SCLK;
    Clocks.DC_CLK   <<  Conn.XCLKIN;
    Clocks.DX_CLK   <<  Conn.EGCK1;
 
// power and NC
    wireall( DSP_VCC, "VCC" );
    DSP_VB  << Conn.VCCINT;
    DSP_VA  << Conn.VCORE;
    wireall( GND );
    for ( int i = 0; i < vc_cdc_count; ++ i )  DSP_VCC << VC_CDC[ i ].POS;
    for ( int i = 0; i < vb_cdc_count; ++ i )  DSP_VB  << VB_CDC[ i ].POS;
    for ( int i = 0; i < va_cdc_count; ++ i )  DSP_VA  << VA_CDC[ i ].POS;
    for ( int i = 0; i < vc_tdc_count; ++ i )  DSP_VCC << VC_TDC[ i ].POS;
    for ( int i = 0; i < vb_tdc_count; ++ i )  DSP_VB  << VB_TDC[ i ].POS;
    for ( int i = 0; i < va_tdc_count; ++ i )  DSP_VA  << VA_TDC[ i ].POS;
 
    "VREF"  <<  Conn.VREF;
    DSP_VCC ^ PullupVREF ^ "VREF" ^ PulldownVREF ^ GND;
 
    "/NC"   << Conn.FM0;  // internal pullup
    "/NC"   << Conn.FM1;  // internal pullup
    GND     << Conn.FM2;
 
 
// DSP JTAG emulation:  FET switch connects TDO to TDI when module is not installed
    "PRESENT" << Conn.PRESENT << SwitchEMU.OE_N ^ PulldownPRESENT ^ GND;
    Conn.TDO  << SwitchEMU.A;
    Conn.TDI  << SwitchEMU.B;
 
    "FINIT_N"  <<  Conn.FINIT_N  ^ PullupFINIT_N  ^ DSP_VCC;
    "EFINIT_N" <<  Conn.EFINIT_N ^ PullupEFINIT_N ^ DSP_VCC;
 
// misc no-connects
    "/NC"  <<  Conn.NC;
    "/NC"  <<  Conn.FDOUT;
    "/NC"  <<  Conn.EFDOUT;
    "/NC"  <<  Conn.CE3_N;
  }
};
 
 
// Host Processing Unit
class CM_HPU : public CM_GPU {
public:
// ***** member bundles ***** //
  CB_CONF2    CONF;      // for FPGA configuration
  CB_JTAG     JTAG;      // for FPGA JTAG
 
// ***** member ports ***** //
  port   GEN;            // XB FPGA generics
  port   EGEN;           // EMIF FPGA generics
 
  port   PRESENT;
  port   RESET_N;
  port   FINIT_N;    // INIT's tell Flash PLD when it is ok to begin FPGA configuration
  port   EFINIT_N;
  port   FDONE;
  port   EFDONE;
 
  port   AOE_N;
  port   ARE_N;
  port   AWE_N;
  port   ARDY;
  port   CE0_N;
  port   CE1_N;
  port   CE2_N;
 
  port     DX0;
  port   CLKX0;
  port   CLKR0;
  port    FSX0;
 
 
// ***** member modules and parts ***** //
  CP_R1K  PullupRESET_N;    // pullup for DSP's RESET_N -- PLD and/or XB FPGA drives RESET_N low
 
  virtual void Register() {
    CM_GPU::Register();
 
// bundles
    reg( CONF );
    reg( JTAG );
 
// ports
    regb( GEN,  76, 0 );
    regb( EGEN, 74, 0 );
 
    reg(  PRESENT     );
    reg(  RESET_N     );
    reg(  FINIT_N     );
    reg(  EFINIT_N    );
    reg(  FDONE       );
    reg(  EFDONE      );
 
    reg(  AOE_N );
    reg(  ARE_N );
    reg(  AWE_N );
    reg(  ARDY  );
    reg(  CE0_N );
    reg(  CE1_N );
    reg(  CE2_N );
 
    reg(    DX0 );
    reg(  CLKX0 );
    reg(  CLKR0 );
    reg(   FSX0 );
 
// parts and modules
    reg( PullupRESET_N );
  }
 
  virtual void Connect() {
    CM_GPU::Connect();
 
    CONF.CCLK        <<  Conn.FCCLK;           // Both FPGA's share a common CCLK and DIN
    CONF.DIN         <<  Conn.FDIN;
    CONF.PROGRAM0_N  <<  Conn.FPROGRAM_N;      // The ROD uses FPROGRAM_N and EFPROGRAM_N to configure each FPGA individually
    CONF.PROGRAM1_N  <<  Conn.EFPROGRAM_N;
 
    GEN       <<  Conn.GEN;
    EGEN      <<  Conn.EGEN;
 
    JTAG.TCK  <<  Conn.FTCK;
    JTAG.TMS  <<  Conn.FTMS;
    JTAG.TDI  <<  Conn.FTDI;
    JTAG.TDO  <<  Conn.FTDO;
 
    RESET_N ^ PullupRESET_N ^ DSP_VCC;  // PLD and/or XB FPGA drives RESET_N low
 
    wire( PRESENT     );     // needed by JTAG subsystem to control FET switch between FTDI and FTDO
    wire( RESET_N     );
    wire( FINIT_N     );
    wire( EFINIT_N    );
    wire( FDONE       );
    wire( EFDONE      );
 
    wire( AOE_N );
    wire( ARE_N );
    wire( AWE_N );
    wire( ARDY  );
    wire( CE0_N );
    wire( CE1_N );
    wire( CE2_N );
 
    wire(   DX0 );
    wire( CLKX0 );
    wire( CLKR0 );
    wire(  FSX0 );
 
    "/NC"  <<  Conn.DR0;
    "/NC"  <<  Conn.CLKS0;
    "/NC"  <<  Conn.FSR0;
  }
};
 
 
// Data Processing Unit
class CM_DPU : public CM_GPU {
public:
// ***** member bundles ***** //
  CB_Half_DC  DC;        // interface to DPU Control subsystem
  CB_Half_DX  DX;        // interface to Data Exchange
 
  CB_CONF2    CONF;      // for FPGA configuration
 
// ***** member ports ***** //
  port   IC_DPU;         // pt-to-pt connections from Interconnect to this DPU
  port   IC_BUS;         // bussed connections from Interconnect to all DPU's in this HalfROD
  port   STRAP;          // 3-bit hard-wired ID number
 
 
// ***** member modules and parts ***** //
  CP_R1K  PulldownRESET_N;  // pulldown for DSP's RESET_N
 
  virtual void Register() {
    CM_GPU::Register();
 
// bundles
    reg( DC );
    reg( DX );
 
    reg( CONF );
 
// ports
    regb( IC_DPU, 24, 0 );
    regb( IC_BUS,  5, 0 );
    regb( STRAP,   2, 0 );
 
// parts and modules
    reg( PulldownRESET_N );
  }
 
  virtual void Connect() {
    CM_GPU::Connect();
 
    CONF.CCLK        <<  Conn.FCCLK;           // Both FPGA's share a common CCLK and DIN
    CONF.DIN         <<  Conn.FDIN;
    CONF.PROGRAM0_N  <<  Conn.FPROGRAM_N;      // The ROD uses FPROGRAM_N and EFPROGRAM_N to configure each FPGA individually
    CONF.PROGRAM1_N  <<  Conn.EFPROGRAM_N;
 
    GND ^ PulldownRESET_N ^ "RESET_N" << Conn.RESET_N;  // XB FPGA drives RESET_N high after configuration
 
    STRAP   << Conn.GEN(  70, 68 );
    IC_DPU  << Conn.GEN(  67, 43 );
    DC.DCC  << Conn.GEN(  42, 32 );
    DC.DCD  << Conn.GEN(  31,  0 );
 
    DX.DXD  << Conn.EGEN( 31,  0 );
    DX.DXC  << Conn.EGEN( 41, 32 );
    IC_BUS  << Conn.EGEN( 47, 42 );
 
    merge( "/NC", Conn.GEN(  76, 71 ) );
    merge( "/NC", Conn.EGEN( 74, 48 ) );
 
    "/NC" << Conn.FTCK;
    "/NC" << Conn.FTMS;
    "/NC" << Conn.FTDI;
    "/NC" << Conn.FTDO;
 
    "/NC" << Conn.FDONE;      // *** DONE does not need a pullup resistor--see BITGEN options to drive DONE ***
    "/NC" << Conn.EFDONE;
    "/NC" << Conn.CE0_N;
    "/NC" << Conn.CE1_N;
    "/NC" << Conn.CE2_N;
    "/NC" << Conn.CE3_N;
 
    "/NC" << Conn.AWE_N;
    "/NC" << Conn.ARE_N;
    "/NC" << Conn.AOE_N;
    "/NC" << Conn.ARDY;
 
    "/NC" << Conn.DX0;     // !! use these? e.g., between pairs of DPU's or as GP I/O
    "/NC" << Conn.DR0;
    "/NC" << Conn.CLKX0;
    "/NC" << Conn.CLKR0;
    "/NC" << Conn.CLKS0;
    "/NC" << Conn.FSX0;
    "/NC" << Conn.FSR0;
 
  }
};
 
#endif