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/*                                                                               *\
                         Copyright (C) 2007 Coolquest, Inc.

      This program is free software; you can redistribute it and/or modify
      it under the terms of the GNU General Public License as published by
      the Free Software Foundation; either version 2 of the License, or
      (at your option) any later version.

      This program is distributed in the hope that it will be useful,
      but WITHOUT ANY WARRANTY; without even the implied warranty of
      MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
      GNU General Public License for more details.

      You should have received a copy of the GNU General Public License along
      with this program; if not, write to the Free Software Foundation, Inc.,
      51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.

    For more about the CBOLD framework and Coolquest, Inc., see www.cbold.com.
\*                                                                               */
 
#include "cb_base.h"
#include "cb_views.h"
#include "cb_xconstraints.h"
#include "cb_dummy_device.h"   // for automated generation of dummy device files for layout application
#include "cb_netlist_al3p.h"   // include desired netlist formatters
#include "cb_netlist_pp.h"
#include "irod.h"
 
 
#pragma argsused
int main( int argc, char* argv[] )
{
 
try {
  TLogStatus Log( cout );
 
  CM_Root Root;          // CM_Root is always the highest-level module of a project
//Root.VerboseNetList = false;   // false --> speed up execution, but Root's TNetList will not contain PinSpec's for Module and Bundle Ports
 
  Log << "Registering";
  reg( Root );         // register highest-level module
 
  Log << "Assigning reference designators";
 
// read in previously assigned designators, if any
  ifstream DSrce;
  OpenFileI( DSrce, DESIGN_NAME "_old_designators.txt" );
  Root.ReadReferenceDesignators( DSrce );
  DSrce.close();
 
  Root.AssignReferenceDesignators();
  Root.CheckReferenceDesignators();                  // check for duplicates
 
#if 1    // >>> write out all designators before layout commences
// write out designators for possible future use
  ofstream DDest;
  OpenFileO( DDest, OUTPUT_BASE "_new_designators.txt" );
  Root.WriteReferenceDesignators( DDest );
  DDest.close();
#endif
 
  Log << "Connecting";
  Root.ConnectAll();   // wire up hierarchy
 
  Log << "Post-Connecting";
  Root.PostConnectAll();         // perform any user-specified post-connect processing
 
  Log << "Creating CAD netlists";
  ofstream NetDest;
  OpenFileO( NetDest, OUTPUT_BASE "_3P.net" );
  OutputCad3P( &Root, NetDest, true );   // output in standard format
  NetDest.close();
  OpenFileO( NetDest, OUTPUT_BASE "_PP.net" );
  OutputCadPP( &Root, NetDest, true );   // output in standard format
  NetDest.close();
 
  Log << "Creating bill of materials";
  ofstream BOM_Dest;
  OpenFileO( BOM_Dest, OUTPUT_BASE "_bom.txt" );
  Root.OutputBOM( BOM_Dest );       // output bill of materials
  BOM_Dest.close();
 
#if 1
  Log << "Creating constraint files";    // output constraint files

  TXConstraints Constraints;

  Constraints.AddIgnorePort( "VCC", "VB", "GND" );
  Constraints.AddIgnorePort( "TCK", "TMS", "TDI", "TDO" );
 
  // Flash Subsystem PLD: do this first, because there are user I/O ports named CCLK and DIN
  Constraints.GenerateConstraintsFile( OUTPUT_BASE "_FlashPldConstraints.ucf",  &Root.VME_Interface.FlashPLD,   &Root.VME_Interface.FlashPLD.Cpld        );
 
  Constraints.AddIgnorePort( "CCLK", "DIN" );  // now ignore CCLK and DIN on the remaining parts
 
  // Host PLD
  Constraints.GenerateConstraintsFile( OUTPUT_BASE "_HostConstraints.ucf",      &Root.Host.HOST_PLD,            &Root.Host.HOST_PLD.Cpld                 );
 
  // VME PLDs
  Constraints.GenerateConstraintsFile( OUTPUT_BASE "_VMECPldConstraints.ucf",   &Root.VME_Interface.VMEC_PLD,   &Root.VME_Interface.VMEC_PLD.Cpld        );
  Constraints.GenerateConstraintsFile( OUTPUT_BASE "_VMEDPldConstraints.ucf",   &Root.VME_Interface.VMED_PLD,   &Root.VME_Interface.VMED_PLD.Cpld        );
 
  // Clock Generation PLDS
  Constraints.GenerateConstraintsFile( OUTPUT_BASE "_NoisyPldConstraints.ucf",  &Root.ClockGeneration.NoisyPLD, &Root.ClockGeneration.NoisyPLD.Cpld      );
  Constraints.GenerateConstraintsFile( OUTPUT_BASE "_QuietPldConstraints.ucf",  &Root.ClockGeneration.QuietPLD, &Root.ClockGeneration.QuietPLD.Cpld      );
 
  Constraints.AddIgnorePort( "PROGRAM_N" );   // NoisyPLD has user I/O ports named PROGRAM_N...
  Constraints.SetPinPrefix( "P" );            // FPGA's in PQFP's require a P before the pin number
 
  // DX FPGAs
  Constraints.GenerateConstraintsFile( OUTPUT_BASE "_DXBFpgaConstraints.ucf",   &Root.DataExchange.DXB_FPGA,    &Root.DataExchange.DXB_FPGA.Fpga.Fpga    );
  Constraints.GenerateConstraintsFile( OUTPUT_BASE "_DXFFpgaConstraints.ucf",   &Root.DataExchange.DXF_FPGA_A,  &Root.DataExchange.DXF_FPGA_A.Fpga.Fpga  );
 
  // Interconnect FPGAs
  Constraints.GenerateConstraintsFile( OUTPUT_BASE "_BPIFpgaConstraints.ucf",   &Root.Interconnect.BPI_FPGA[0], &Root.Interconnect.BPI_FPGA[0].Fpga.Fpga );
  Constraints.GenerateConstraintsFile( OUTPUT_BASE "_TTCFpgaConstraints.ucf",   &Root.Interconnect.TTC_FPGA,    &Root.Interconnect.TTC_FPGA.Fpga.Fpga    );
 
  // DPU Control FPGA
  Constraints.GenerateConstraintsFile( OUTPUT_BASE "_DCFpgaConstraints.ucf",    &Root.DPU_Control.DC_FPGA,      &Root.DPU_Control.DC_FPGA.Fpga.Fpga      );
#endif
 
 
#if 1    // **** warning ****  the specified device file directory must already exist
  Log << "Creating device files";
  MakeDeviceFiles( &Root, "DeviceFiles" );
#endif
 
 
  Log << "Creating symbolic netlist";
  ofstream View1_Dest;
  OpenFileO( View1_Dest, OUTPUT_BASE "_SymNetlist.txt" );
  TViewSymbolicNetlist View1;
  View1.ShowAllPins = true;
  View1.SetBriefNetLimit( 4 );   // output entire net if less than 4 connections, else output net name only

#if 0     // list some nets in non-verbose format -- no longer needed -- see TViewSymbolicNetlist::SetBriefNetLimit
  View1.AddBriefNet( "/NC", "GND" );
  View1.AddBriefNet( "BPWR_VPOS5", "BPWR_VPOS3_3", "VCC5A" );
  View1.AddBriefNet( "MB_VCC5", "MB_VCC",  "VB" );
  View1.AddBriefNet(           "DSP_VCC", "DSP_VA" );
  View1.AddBriefNet( "VREF" );
  View1.AddBriefNet( "A_DCD", "B_DCD" );
  View1.AddBriefNet( "A_DCC", "B_DCC" );
  View1.AddBriefNet( "A_DXD", "B_DXD" );
  View1.AddBriefNet( "A_DXC", "B_DXC" );
  View1.AddBriefNet( "INTER_DX" );
  View1.AddBriefNet( "EMU0", "EMU1" );
  View1.AddBriefNet( "BA", "BDF", "BDG", "BDH" );
  View1.AddBriefNet( "SOFTRESET_N" );
  View1.AddBriefNet( "FP_CKOE_DIPSW" );
  View1.AddBriefNet( "SD", "SYNSEL_CD" );
  View1.AddBriefNet( "DIN_MB", "DIN_A", "DIN_B" );
  View1.AddBriefNet( "TRST_N" );
  View1.AddBriefNet( "A_IC_BUS", "B_IC_BUS" );
  View1.AddBriefNet( "FP_EMULATOR_TMS" );
  View1.AddBriefNet( "BUF_JTMS", "JTMS" );
  View1.AddBriefNet( "SW5_DVA", "SW5_VB" );
  View1.AddBriefNet( "OE_N_BIAS_A", "VPC", "ABUFOE_N", "DBUFOE_N", "ABUFDIR", "DBUFDIR" );
  View1.AddBriefNet( "VME_GA_N" );
#endif
 
  View1.Dump( View1_Dest, &Root );                      // ouput symbolic netlist view: parts and nets
  View1_Dest.close();
 
  OpenFileO( View1_Dest, OUTPUT_BASE "_SymNets.txt" );
  View1.DumpNets( View1_Dest, &Root );                  // ouput symbolic view: nets only
  View1_Dest.close();
 
  OpenFileO( View1_Dest, OUTPUT_BASE "_SymBriefNets.txt" );
  View1.DumpBriefNets( View1_Dest, &Root );             // ouput symbolic view: brief nets only
  View1_Dest.close();
 
  OpenFileO( View1_Dest, OUTPUT_BASE "_SymParts.txt" );
  View1.DumpParts( View1_Dest, &Root );                 // ouput symbolic view: parts only
  View1_Dest.close();
 
  OpenFileO( View1_Dest, OUTPUT_BASE "_SymModules.txt" );
  View1.DumpModules( View1_Dest, &Root );               // ouput symbolic view: modules only
  View1_Dest.close();
 
//View1.SetBriefPathChar( '_' );   // enable brief paths in part connection lists
  OpenFileO( View1_Dest, OUTPUT_BASE "_SymNetlist.html" );
  View1.DumpHTML( View1_Dest, &Root );                  // ouput symbolic view: HTML version
  View1_Dest.close();
 
#if 1
  Log << "Creating layout script files";                // output script (.do) files
  TGenLayoutScript LayoutScript;
  LayoutScript.GenerateScriptFile( &Root );
#endif
 
     Log << "Creating netlist dump";
     ofstream                NetDumpDest;
     OpenFileO(              NetDumpDest, OUTPUT_BASE "_NetlistDump.txt" );
     Root.DumpSortedNetList( NetDumpDest, true );      // true --> dump all, including PinSpec's for non-part ports
     NetDumpDest.close();
 
     Log << "Creating database dump";
     ofstream          Dest;
     OpenFileO(        Dest, OUTPUT_BASE "_DatabaseDump.txt" );
     Root.DumpGlobals( Dest );
     Root.DumpAll(     Dest );
     Root.DumpNetList( Dest );
 
     TSubBusList NonListed;
     Root.AddNonListedPortRanges( &NonListed );
     Dest << "\n\nThe entire range of all ports should be listed (i.e., connected):";
     Dest <<   "\n  Ports of TParts and TModules should be listed in the Part/Module's Owner's SubBusList or the Global SubBusList.";
     Dest <<   "\n  Ports of TModules should also be listed in the Module's SubBusList, unless they are listed in the Global SubBusList.";
     Dest <<   "\n  Ports of TBundle's are similar to ports of their ultimate owner TModule.";
 
 
     Dest <<   "\n\nTotal nonconforming port ranges: " << NonListed.GetSubBusCount();
     if ( NonListed.GetSubBusCount() ) {
       Dest << " (listed below).\n";
       NonListed.DumpAll( Dest );
     }
 
     TNet NonWired;                              // form net containing all non-wired pins
     Root.AddNonWiredPins( &NonWired );
     Dest << "\n\nNon-wired pins:";
     NonWired.DumpAsPortRanges( Dest );          // dump as PortRange's (rather than PinSpec's) for readability
 
     Dest << "\n\nSingle-node nets:";
     int SingleNodeNets = Root.DumpSingleNodeNets( Dest );
 
     Dest << "\n\nNo-connect net ("  <<  NoConnect  <<  "):";
     int NoConnects = Root.DumpNoConnectNet( Dest );
 
     Dest << "\n";
     Dest << "\nTotal nonconforming port ranges: "   << NonListed.GetSubBusCount() << ".";
     Dest << "\nTotal non-wired PinSpecs:  "         << NonWired.GetPinSpecCount() << ".";
     Dest << "\nTotal single-node nets:  "           << SingleNodeNets             << ".";
     Dest << "\nTotal PinSpecs in no-connect net:  " << NoConnects                 << ".";
     Dest << "\nTotal Nets:  "                       << Root.GetNetCount()         << ".";
 
     Dest << "\n\nEnd of Dump\n";
     Dest.close();
 
 
   Log.End();
   cout   << "\nTotal nonconforming port ranges: "   << NonListed.GetSubBusCount() << ".";
   cout   << "\nTotal non-wired PinSpecs:  "         << NonWired.GetPinSpecCount() << ".";
   cout   << "\nTotal single-node nets:  "           << SingleNodeNets             << ".";
   cout   << "\nTotal PinSpecs in no-connect net:  " << NoConnects                 << ".";
   cout   << "\nTotal Nets:  "                       << Root.GetNetCount()         << ".";
   cout   << "\n";
 
   if ( argc == 1 ) {         // any command line argument disables the terminal user prompt
     cout   << "\nPress Enter to continue.\n" << flush;
     cin.get();
   }
 
}
catch ( string& aString ) {
  cout << "\n\nError:  " << aString << '\n';
  MessageIfError( cout, TModPar::RegisteringModPar,    "registering"     );
  MessageIfError( cout, TModPar::PostConnectingModPar, "post-connecting" );
  MessageIfError( cout, TModule::ConnectingModule,     "connecting"      );
 
  cin.get();
  return 1;    // error
}
 
  return 0;    // no error
}

 

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