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C++BOLD Example Design: IROD

// THIS FILE IS IN THE PUBLIC DOMAIN.
// IT IS PROVIDED AS IS WITHOUT WARRANTY OF ANY KIND, EITHER EXPRESSED OR IMPLIED, INCLUDING, BUT
// NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE.
 
#ifndef _IrodH_
#define _IrodH_
 
#include "cb_base.h"
#include "cb_shorthand.h"
 
// above:  standard code
// below:  design-specific code
 
// Search all files for ">>>" to find important comments.
 
// file paths, etc
#define  DESIGN_NAME  "irod"                                                                // name of design--used primarily to form file names
//                    dir for all CBOLD output  subdir. for this design   base of file name
#define  OUTPUT_BASE  OUTPUT_PATH DIR_SEP       DESIGN_NAME DIR_SEP       DESIGN_NAME        // concatenation of path and name --> base for output file names
 
#include "irod_prop.h"
 
// files needed by many of the subsystems
#include "rod_clones.h"     // cloned resisters, capacitors, etc.
#include "decoupling.h"
 
const int DPU_HalfCount = 6;   // number of DPU's in a HalfROD
 
// subsystems
#include "backplane.h"
#include "clock_generation.h"
#include "data_exchange.h"
#include "dpu_control.h"
#include "front_panel.h"
#include "half_rod.h"
#include "host.h"
#include "interconnect.h"
#include "jtag.h"
#include "power.h"
#include "vme_interface.h"

// ************  IROD  ************
// subsystem           abbreviation
// ------------        ------------
//   Backplane           BK or Back (BP within the Clock Generation subsytem)
//   ClockGeneration     CG
//   DataExchange        DX
//   DPU_Control         DC
//   FrontPanel          FP or Front
//   HalfROD             Half
//     Half A            A
//     Half B            B
//   Host                HO or Host
//   Interconnect        IC
//   JTAG                JT or JTAG
//   Power               PW or PWR
//   VME_Interface       VM or VME
 
 
class CM_Root : public TRootModule {
public:
// root-level module has no ports
 
// instantiate subsystems
  CM_Backplane        Backplane;
  CM_ClockGeneration  ClockGeneration;
  CM_DataExchange     DataExchange;
  CM_DPU_Control      DPU_Control;
  CM_FrontPanel       FrontPanel;
  CM_HalfROD          Half_A;
  CM_HalfROD          Half_B;
  CM_Host             Host;
  CM_Interconnect     Interconnect;
  CM_JTAG             JTAG;
  CM_Power            Power;
  CM_VME_Interface    VME_Interface;
 
 
  virtual void Register() {  
// subsystems                                               // first few letters of reference designators
    reg( Backplane       );  Backplane.SetReferenceBase(       "BK" );
    reg( ClockGeneration );  ClockGeneration.SetReferenceBase( "CG" );
    reg( DataExchange    );  DataExchange.SetReferenceBase(    "DX" );
    reg( DPU_Control     );  DPU_Control.SetReferenceBase(     "DC" );
    reg( FrontPanel      );  FrontPanel.SetReferenceBase(      "FP" );
    reg( Half_A          );  Half_A.SetReferenceBase(          "A"  );  // see CM_HalfROD for more ReferenceBase's
    reg( Half_B          );  Half_B.SetReferenceBase(          "B"  );
    reg( Host            );  Host.SetReferenceBase(            "HO" );
    reg( Interconnect    );  Interconnect.SetReferenceBase(    "IC" );
    reg( JTAG            );  JTAG.SetReferenceBase(            "JT" );
    reg( Power           );  Power.SetReferenceBase(           "PW" );
    reg( VME_Interface   );  VME_Interface.SetReferenceBase(   "VM" );
  }
 
  virtual void Connect() {
 
// *** connect subsystem ports (except JTAG and power ports) *** //
 
  // net names to override subsequently assigned net names
    "BA"     <<  Host.BA;
    "BDF"    <<  Host.BDF;
    "BDG"    <<  Host.BDG;
    "BDH"    <<  Host.BDH;
 
 
  // Backplane
    "BPWR_"  <<  Backplane.Power   <<  Power.BK;
    "BK_"    <<  Backplane.CG      <<  ClockGeneration.BK;
    ""       <<  Backplane.DX      <<  DataExchange.BK;
    ""       <<  Backplane.HO      <<  Host.BK;
    ""       <<  Backplane.IC      <<  Interconnect.BK;
    "VME_"   <<  Backplane.VMEbus  <<  VME_Interface.VMEbus;
 
    
  // ClockGeneration
    "DX_"    <<  ClockGeneration.DX   <<   DataExchange.CG;
    "DC_"    <<  ClockGeneration.DC   <<    DPU_Control.CG;
    "A_"     <<  ClockGeneration.A    <<         Half_A.CG;
    "B_"     <<  ClockGeneration.B    <<         Half_B.CG;
    "FP_"    <<  ClockGeneration.FP   <<     FrontPanel.CG;
    "HO_"    <<  ClockGeneration.HO   <<           Host.CG;
    "IC_"    <<  ClockGeneration.IC   <<   Interconnect.CG;
    "VME_"   <<  ClockGeneration.VME  <<  VME_Interface.CG;
    ""       <<  ClockGeneration.PWR  <<          Power.CG;
 
 
  // DataExchange
     "A_"    <<  DataExchange.A   <<  Half_A.DX;
     "B_"    <<  DataExchange.B   <<  Half_B.DX;
     "HDX_"  <<  DataExchange.H   <<    Host.DX;
 
  // DPU_Control
     "A_"    <<  DPU_Control.A    <<  Half_A.DC;  // DCD and DCC
     "B_"    <<  DPU_Control.B    <<  Half_B.DC;
     ""      <<  DPU_Control.HO   <<    Host.DC;  // DCD_H and DCC_H -- not quite analogous to DCD and DCC
 
  // FrontPanel
     "FP_"   <<  FrontPanel.IC    <<  Interconnect.FP;
     "FP_"   <<  FrontPanel.VME   <<  VME_Interface.FP;
 
  // Interconnect
     "A_"    <<  Interconnect.A   <<  Half_A.IC;
     "B_"    <<  Interconnect.B   <<  Half_B.IC;
     "HIC_"  <<  Interconnect.HO  <<  Host.IC;
 
  // Half_A
  // Half_B
  // Host
    ""       <<  Host.VME         <<  VME_Interface.HO;
 
  // Power
    "PC_"    <<  Power.VME        <<  VME_Interface.PWR;    // power is under VME control
    "MC_"    <<  Power.MeasCtrl   <<  Host.MeasCtrl;        // power measurement is under Host control
 
  // VME_Interface
  // no additional connections
 
// *** connect JTAG ***
   "EMU0"     <<  JTAG.HO.HPU_DSP.EMU0;       // override any net names subsequently assigned
   "EMU1"     <<  JTAG.HO.HPU_DSP.EMU1;
   "TRST_N"   <<  JTAG.HO.HPU_DSP.TRST_N;
   "FP_"      <<  JTAG.FP  <<  FrontPanel.JT;
 
   // use net names assigned above or within CM_JTAG
 
   JTAG.BK    <<  Backplane.JT;
   JTAG.CG    <<  ClockGeneration.JT;
   JTAG.DC    <<  DPU_Control.JT;
   JTAG.DX    <<  DataExchange.JT;
   JTAG.A     <<  Half_A.JT;
   JTAG.B     <<  Half_B.JT;
   JTAG.HO    <<  Host.JT;
   JTAG.IC    <<  Interconnect.JT;
   JTAG.VME   <<  VME_Interface.JT;
 

// *** connect supply ports ***
    "VB" << Power.VB;            // >>> MB_VB and DSP_VB are now a single voltage, VB
    wireall( "VB", "MB_VB"   );
    wireall( "VB", "DSP_VB"  );
 
    wireall( "MB_VCC5" );   // motherboard
    wireall( "MB_VCC"  );
    wireall( "VPC"     );   // bus precharge voltage, used only by VME transceivers
 
    wireall( "DSP_VCC" );   // DSP modules
    wireall( "DSP_VA"  );
 
    wireall( "GND" );
 
  }
};
 
#endif