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C++BOLD Example Design: IROD

// THIS FILE IS IN THE PUBLIC DOMAIN.
// IT IS PROVIDED AS IS WITHOUT WARRANTY OF ANY KIND, EITHER EXPRESSED OR IMPLIED, INCLUDING, BUT
// NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE.
 
#ifndef _NoisyPLDH_
#define _NoisyPLDH_
 
#include "xc95144xl_100.h"
 
class CM_NoisyPLD : public TModule {    // PLD for Clock Generation subsystem
public:
// ***** member bundles ***** //
  CB_JTAG  JTAG;
 
// ***** member ports ***** //
  port VCC;         // 3.3V
  port GND;
  port SOFTRESET_N;
                    // Host EMIF bus
  port  D;          // 8 data
  port  A;          // 2 address
  port  NSTB_N;     // strobe to NoisyPLD
  port  WR_N;
 
  port  QD;         // quiet versions of Host EMIF bus, to QuietPLD
  port  QA;
  port  QWR_N;
  port  QSTB_N;
 
  port  BASE_CLK;   // 25 MHz input clock
  port  BOOT_CLK;   // 6.25 MHz output clock used to bootstrap HPU
 
  port  MEAS_IN;    // clock inputs for frequency measurement 10
  port  PROGRAM_N;  // FPGA configuration signals, one for each FPGA in the ROD except HPU FPGA's
 
 
// ***** member modules and parts ***** //
  CP_XC95144XL_100  Cpld;
 
 
  // decoupling
  enum { vc_cdc_count =  4,
         vc_tdc_count =  1 };
  CP_CDC_POS  VC_CDC[ vc_cdc_count ];    // ceramic decoupling
  CP_TDC_POS  VC_TDC[ vc_tdc_count ];    // tantalum decoupling
 
 
  virtual void Register() {
// bundles
    reg( JTAG );
 
// ports
    reg(  VCC      );
    reg(  GND      );
    reg(  SOFTRESET_N  );
 
    regb( D, 7, 0  );
    regb( A, 1, 0  );
    reg(  NSTB_N   );
    reg(  WR_N     );
 
    regb( QD, 7, 0 );
    reg(  QA       );
    reg(  QWR_N    );
    reg(  QSTB_N   );
 
    reg(  BASE_CLK );
    reg(  BOOT_CLK );
 
    regb( MEAS_IN,    9, 0 );
    regb( PROGRAM_N, 36, 0 );
 
 
 
// parts and modules
    reg(  Cpld );
    rega( VC_CDC, vc_cdc_count );
    rega( VC_TDC, vc_tdc_count );
 
  }
 
  virtual void Connect() {
    wireall( GND );
    wire(    VCC );
    VCC << Cpld.VCCIO;
    for ( int i = 0; i < vc_cdc_count; ++ i )  VCC << VC_CDC[ i ].POS;
    for ( int i = 0; i < vc_tdc_count; ++ i )  VCC << VC_TDC[ i ].POS;
 
    wire( JTAG, Cpld );
 
  //User I/O
    BOOT_CLK          <<  Cpld.IO1_GTS3;   // output clock:  BASE_CLK/4
    NSTB_N            <<  Cpld.IO2_GTS4;   // avoid possible HDL synthesizer confusion
    "/NC"             <<  Cpld.IO3_GTS1;
    "/NC"             <<  Cpld.IO4_GTS2;
 
    int i = 0;
    PROGRAM_N( i++ )  <<  Cpld.IO6;       // PROGRAM_N starts configuration of FPGA
    PROGRAM_N( i++ )  <<  Cpld.IO7;
    PROGRAM_N( i++ )  <<  Cpld.IO8;
    PROGRAM_N( i++ )  <<  Cpld.IO9;
    PROGRAM_N( i++ )  <<  Cpld.IO10;
    PROGRAM_N( i++ )  <<  Cpld.IO11;
    PROGRAM_N( i++ )  <<  Cpld.IO12;
    PROGRAM_N( i++ )  <<  Cpld.IO13;
    PROGRAM_N( i++ )  <<  Cpld.IO14;
    PROGRAM_N( i++ )  <<  Cpld.IO15;
    PROGRAM_N( i++ )  <<  Cpld.IO16;
    PROGRAM_N( i++ )  <<  Cpld.IO17;
    PROGRAM_N( i++ )  <<  Cpld.IO18;
    PROGRAM_N( i++ )  <<  Cpld.IO19;
 
    "/NC"             <<  Cpld.IO20;
    BASE_CLK          <<  Cpld.IO22_GCK1;
    NSTB_N            <<  Cpld.IO23_GCK2;
    WR_N              <<  Cpld.IO24;
 
    PROGRAM_N( i++ )  <<  Cpld.IO25;
 
    "MEAS_OUT"        <<  Cpld.IO27_GCK3;    // clock being measured
    "MEAS_OUT"        <<  Cpld.IO28;         // avoid possible HDL synthesizer confusion
 
    PROGRAM_N( i++ )  <<  Cpld.IO29;
    PROGRAM_N( i++ )  <<  Cpld.IO30;
    PROGRAM_N( i++ )  <<  Cpld.IO32;
    PROGRAM_N( i++ )  <<  Cpld.IO33;
    PROGRAM_N( i++ )  <<  Cpld.IO34;
    PROGRAM_N( i++ )  <<  Cpld.IO35;
    PROGRAM_N( i++ )  <<  Cpld.IO36;
    PROGRAM_N( i++ )  <<  Cpld.IO37;
    PROGRAM_N( i++ )  <<  Cpld.IO39;
    PROGRAM_N( i++ )  <<  Cpld.IO40;
    PROGRAM_N( i++ )  <<  Cpld.IO41;
    PROGRAM_N( i++ )  <<  Cpld.IO42;
    PROGRAM_N( i++ )  <<  Cpld.IO43;
    PROGRAM_N( i++ )  <<  Cpld.IO46;
    PROGRAM_N( i++ )  <<  Cpld.IO49;
    PROGRAM_N( i++ )  <<  Cpld.IO50;
    PROGRAM_N( i++ )  <<  Cpld.IO52;
    PROGRAM_N( i++ )  <<  Cpld.IO53;
    PROGRAM_N( i++ )  <<  Cpld.IO54;
    PROGRAM_N( i++ )  <<  Cpld.IO55;
    PROGRAM_N( i++ )  <<  Cpld.IO56;
    PROGRAM_N( i++ )  <<  Cpld.IO58;
    "/NC"             <<  Cpld.IO59;
 
    i = 0;
    MEAS_IN( i++ )  <<  Cpld.IO60;
    MEAS_IN( i++ )  <<  Cpld.IO61;
    MEAS_IN( i++ )  <<  Cpld.IO63;
    MEAS_IN( i++ )  <<  Cpld.IO64;
    MEAS_IN( i++ )  <<  Cpld.IO65;
    MEAS_IN( i++ )  <<  Cpld.IO66;
    MEAS_IN( i++ )  <<  Cpld.IO67;
    MEAS_IN( i++ )  <<  Cpld.IO68;
    MEAS_IN( i++ )  <<  Cpld.IO70;
    MEAS_IN( i++ )  <<  Cpld.IO71;
    "/NC"           <<  Cpld.IO72;
 
    i = 0;
    D( i++ )   <<  Cpld.IO73;
    D( i++ )   <<  Cpld.IO74;   // bus from Host
    D( i++ )   <<  Cpld.IO76;
    D( i++ )   <<  Cpld.IO77;
    D( i++ )   <<  Cpld.IO78;
    D( i++ )   <<  Cpld.IO79;
    D( i++ )   <<  Cpld.IO80;
    D( i++ )   <<  Cpld.IO81;
    A( 0 )     <<  Cpld.IO82;
    A( 1 )     <<  Cpld.IO85;
 
    i = 0;
    QD( i++ )  <<  Cpld.IO86;   // bus to Quiet PLD
    QD( i++ )  <<  Cpld.IO87;
    QD( i++ )  <<  Cpld.IO89;
    QD( i++ )  <<  Cpld.IO90;
    QD( i++ )  <<  Cpld.IO91;
    QD( i++ )  <<  Cpld.IO92;
    QD( i++ )  <<  Cpld.IO93;
    QD( i++ )  <<  Cpld.IO94;
    QA         <<  Cpld.IO95;
    QSTB_N     <<  Cpld.IO96;
    QWR_N      <<  Cpld.IO97;
 
    SOFTRESET_N  <<  Cpld.IO99_GSR;
  }
};
 
#endif