CBOLD IROD Example Design: quiet

Coolquest, Inc.
C⁺⁺BOLD Example Design: IROD
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// THIS FILE IS IN THE PUBLIC DOMAIN.
// IT IS PROVIDED AS IS WITHOUT WARRANTY OF ANY KIND, EITHER EXPRESSED OR IMPLIED, INCLUDING, BUT
// NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE.
 
#ifndef _QuietPLDH_
#define _QuietPLDH_
 
#include "xc95144xl_100.h"
 
class CM_QuietPLD : public TModule {    // PLD for Clock Generation subsystem
public:
// ***** member bundles ***** //
  CB_JTAG  JTAG;
 
// ***** member ports ***** //
  port VCC;         // 3.3V
  port GND;
  port SOFTRESET_N;
 
  port  QD;              // quiet versions of Host EMIF bus, from Noisy PLD
  port  QA;
  port  QWR_N;
  port  QSTB_N;
 
  port  IRCLK;          // clocks from which SYN_BASE can be derived
  port  ISCLK;
  port  ITCLK;
 
  port  DERIVED_BASE;    // one of the above clock inputs divided down
 
                         // address bits for primary multiplexers
  port  MuxA_RCLK;       //   2 bits
  port  MuxA_SCLK;       //   2
  port  MuxA_TCLK;       //   2
  port  MuxA_DCLK;       //   2
  port  MuxA_DC_CLK;     //   2
  port  MuxA_DX_CLK;     //   2
  port  MuxA_HPU_CLK;    //   1
  port  MuxA_SYN_BASE;   //   1
                         // address bits for secondary multiplexers
  port  SMuxA_RCLK;      //   2 bits
  port  SMuxA_TCLK;      //   2
                         // frequency selects for multipliers
  port  MpyFS_IRCLK;     //   2 bits
  port  MpyFS_ISCLK;     //   2
  port  MpyFS_ITCLK;     //   2
 
  port  DrvSCK_IRCLK;    // serial clocks for CDC319 drivers
  port  DrvSCK_ISCLK;
  port  DrvSCK_ITCLK;
  port  DrvSCK_SYN_BASE;
 
  port  SynSCK_RCLK;     // synthesizer serial clocks
  port  SynSCK_SCLK;
  port  SynSCK_TCLK;
  port  SynSCK_DCLK;
  port  SynSCK_DC_CLK;
  port  SynSCK_DX_CLK;
  port  SynSCK_HPU_CLK;
  port  SynSCK_DPU_CLK;
  port  SynSCK_DXINT_CLK;
 
  port  SynSEL_CD;       // synthesizer SEL_CD, to all synthesizers
 
  port  SD;              // serial data, to all synthesizers and CDC319 drivers
  port  OscOE_HPU;       // output enables for HPU oscillators
 
 
// ***** member modules and parts ***** //
  CP_XC95144XL_100  Cpld;
 
 
  // decoupling
  enum { vc_cdc_count =  4,
         vc_tdc_count =  1 };
  CP_CDC_POS  VC_CDC[ vc_cdc_count ];    // ceramic decoupling
  CP_TDC_POS  VC_TDC[ vc_tdc_count ];    // tantalum decoupling
 
 
  virtual void Register() {
// bundles
    reg( JTAG );
 
// ports
    reg(  VCC      );
    reg(  GND      );
    reg(  SOFTRESET_N  );
 
    regb( QD, 7, 0 );
    reg(  QA       );
    reg(  QWR_N    );
    reg(  QSTB_N   );
 
    reg(  IRCLK );
    reg(  ISCLK );
    reg(  ITCLK );
 
    reg(  DERIVED_BASE );
 
    regb( MuxA_RCLK,   1, 0 );   //   2 bits
    regb( MuxA_SCLK,   1, 0 );   //   2
    regb( MuxA_TCLK,   1, 0 );   //   2
    regb( MuxA_DCLK,   1, 0 );   //   2
    regb( MuxA_DC_CLK, 1, 0 );   //   2
    regb( MuxA_DX_CLK, 1, 0 );   //   2
    reg(  MuxA_HPU_CLK      );   //   1
    reg(  MuxA_SYN_BASE     );   //   1
 
    regb( SMuxA_RCLK,  1, 0 );   //   2 bits
    regb( SMuxA_TCLK,  1, 0 );   //   2
 
    regb( MpyFS_IRCLK, 1, 0 );   //   2 bits
    regb( MpyFS_ISCLK, 1, 0 );   //   2
    regb( MpyFS_ITCLK, 1, 0 );   //   2
 
    reg(  DrvSCK_IRCLK      );
    reg(  DrvSCK_ISCLK      );
    reg(  DrvSCK_ITCLK      );
    reg(  DrvSCK_SYN_BASE   );
 
    reg(  SynSCK_RCLK );
    reg(  SynSCK_SCLK );
    reg(  SynSCK_TCLK );
    reg(  SynSCK_DCLK );
    reg(  SynSCK_DC_CLK     );
    reg(  SynSCK_DX_CLK     );
    reg(  SynSCK_HPU_CLK    );
    reg(  SynSCK_DPU_CLK    );
    reg(  SynSCK_DXINT_CLK  );
 
    reg(  SynSEL_CD );
 
    reg(  SD );
    reg(  OscOE_HPU  );
 
// parts and modules
    reg(  Cpld );
    rega( VC_CDC, vc_cdc_count );
    rega( VC_TDC, vc_tdc_count );
  }
 
  virtual void Connect() {
    wireall( GND );
    wire(    VCC );
    VCC << Cpld.VCCIO;
 
    for ( int i = 0; i < vc_cdc_count; ++ i )  VCC << VC_CDC[ i ].POS;
    for ( int i = 0; i < vc_tdc_count; ++ i )  VCC << VC_TDC[ i ].POS;
 
    wire( JTAG, Cpld );
 
    "/NC"         <<  Cpld.IO1_GTS3;
    "/NC"         <<  Cpld.IO2_GTS4;
 
    "QGTS"        <<  Cpld.IO3_GTS1;      // may be helpful for readback
    "QGTS"        <<  Cpld.IO4_GTS2;
 
    "/NC"         <<  Cpld.IO6;
    "/NC"         <<  Cpld.IO7;
 
    IRCLK         <<  Cpld.IO8;
    ISCLK         <<  Cpld.IO9;
    ITCLK         <<  Cpld.IO10;
 
    "/NC"         <<  Cpld.IO11;
 
    OscOE_HPU     <<  Cpld.IO12;
 
    "/NC"         <<  Cpld.IO13;
    "/NC"         <<  Cpld.IO14;
    "/NC"         <<  Cpld.IO15;
 
    DERIVED_BASE  <<  Cpld.IO16;
 
    "/NC"         <<  Cpld.IO17;
    "/NC"         <<  Cpld.IO18;
 
    SynSEL_CD     <<  Cpld.IO19;
    "/NC"         <<  Cpld.IO20;
 
    "/NC"         <<  Cpld.IO22_GCK1;
 
    QSTB_N        <<  Cpld.IO23_GCK2;
 
    "/NC"         <<  Cpld.IO24;
    "/NC"         <<  Cpld.IO25;
 
    "DERIVED_OUT"     <<  Cpld.IO27_GCK3;    // clock to be divided to get DERIVED_BASE
    "DERIVED_OUT"     <<  Cpld.IO28;         // avoid possible HDL synthesizer confusion
 
    "/NC"             <<  Cpld.IO29;
    "/NC"             <<  Cpld.IO30;
 
    SD                <<  Cpld.IO32;
 
    MuxA_RCLK( 0 )    <<  Cpld.IO33;
    MuxA_RCLK( 1 )    <<  Cpld.IO34;
    MuxA_SCLK( 0 )    <<  Cpld.IO35;
    MuxA_SCLK( 1 )    <<  Cpld.IO36;
    MuxA_TCLK( 0 )    <<  Cpld.IO37;
    MuxA_TCLK( 1 )    <<  Cpld.IO39;
    MuxA_DCLK( 0 )    <<  Cpld.IO40;
    MuxA_DCLK( 1 )    <<  Cpld.IO41;
    MuxA_DC_CLK( 0 )  <<  Cpld.IO42;
    MuxA_DC_CLK( 1 )  <<  Cpld.IO43;
    MuxA_DX_CLK( 0 )  <<  Cpld.IO46;
    MuxA_DX_CLK( 1 )  <<  Cpld.IO49;
    MuxA_HPU_CLK      <<  Cpld.IO50;
    MuxA_SYN_BASE     <<  Cpld.IO52;
 
    SMuxA_RCLK( 0 )   <<  Cpld.IO53;
    SMuxA_RCLK( 1 )   <<  Cpld.IO54;
    SMuxA_TCLK( 0 )   <<  Cpld.IO55;
    SMuxA_TCLK( 1 )   <<  Cpld.IO56;
    "/NC"             <<  Cpld.IO58;
    "/NC"             <<  Cpld.IO59;
 
    MpyFS_IRCLK( 0 )  <<  Cpld.IO60;
    MpyFS_IRCLK( 1 )  <<  Cpld.IO61;
    MpyFS_ISCLK( 0 )  <<  Cpld.IO63;
    MpyFS_ISCLK( 1 )  <<  Cpld.IO64;
    MpyFS_ITCLK( 0 )  <<  Cpld.IO65;
    MpyFS_ITCLK( 1 )  <<  Cpld.IO66;
 
 
    DrvSCK_IRCLK      <<  Cpld.IO67;
    DrvSCK_ISCLK      <<  Cpld.IO68;
    DrvSCK_ITCLK      <<  Cpld.IO70;
    DrvSCK_SYN_BASE   <<  Cpld.IO71;
 
    SynSCK_RCLK       <<  Cpld.IO72;
    SynSCK_SCLK       <<  Cpld.IO73;
    SynSCK_TCLK       <<  Cpld.IO74;
    SynSCK_DCLK       <<  Cpld.IO76;
    SynSCK_DC_CLK     <<  Cpld.IO77;
    SynSCK_DX_CLK     <<  Cpld.IO78;
    SynSCK_HPU_CLK    <<  Cpld.IO79;
    SynSCK_DPU_CLK    <<  Cpld.IO80;
    SynSCK_DXINT_CLK  <<  Cpld.IO81;
 
    "/NC"             <<  Cpld.IO82;
    "/NC"             <<  Cpld.IO85;
 
    int i = 0;
    QD( i++ )  <<  Cpld.IO86;   // bus from Noisy PLD
    QD( i++ )  <<  Cpld.IO87;
    QD( i++ )  <<  Cpld.IO89;
    QD( i++ )  <<  Cpld.IO90;
    QD( i++ )  <<  Cpld.IO91;
    QD( i++ )  <<  Cpld.IO92;
    QD( i++ )  <<  Cpld.IO93;
    QD( i++ )  <<  Cpld.IO94;
 
    QA           <<  Cpld.IO95;
    QSTB_N       <<  Cpld.IO96;     // avoid possible HDL synthesizer confusion
    QWR_N        <<  Cpld.IO97;
    SOFTRESET_N  <<  Cpld.IO99_GSR;
  }
};
 
#endif
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