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C++BOLD Example Design: IROD

// THIS FILE IS IN THE PUBLIC DOMAIN.
// IT IS PROVIDED AS IS WITHOUT WARRANTY OF ANY KIND, EITHER EXPRESSED OR IMPLIED, INCLUDING, BUT
// NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE.
 
#ifndef _STD_DRIVERSH_
#define _STD_DRIVERSH_
 
#include "clockdriverscdc.h"
 
// User must provide decoupling capacitors for these classes:
//   CM_STD_CDC319
 
class CM_STD_CDC319 : public TModule {    // base class for CDC319 + series terminators
 
public:
// ***** member bundles ***** //
 
// ***** member ports ***** //
                // same ports as CP_CDC319
  port VCC;     // 3.3V
  port GND;
  port OUT;
  port IN;
  port OE;
  port SCLOCK;
  port SDATA;
 
 
 
// ***** member modules and parts ***** //
 
  CP_CDC319       Drv;
                               // series termination resistor packs
  CP_EXB2HV560JV  Term1;      // 8 isolated resistors, 3 unused
  CP_EXB2HV560JV  Term2;
 
 
  virtual void Register() {
// ports
    reg(  VCC    );
    reg(  GND    );
    regb( OUT, 9, 0 );
    reg(  IN     );
    reg(  OE     );
    reg(  SCLOCK );
    reg(  SDATA  );
 
// parts and modules
    reg(  Drv );
    reg(  Term1 );
    reg(  Term2 );
  }
 
  virtual void Connect() {
    wire( VCC );
    wire( GND );
 
    wire( IN );        // direct connections to CDC319
    wire( OE );
    wire( SCLOCK );
    wire( SDATA  );
 
    "LOCAL"  << Drv.OUT;  // give local signals a name
 
// wire outputs via series resistors, with ordering optimized for layout
 
    OUT( 9 ) << Term1.A( 0 );  Drv.OUT( 9 ) << Term1.B( 0 );  // >>> place resistor packs on same side as CDC319
    OUT( 8 ) << Term1.A( 1 );  Drv.OUT( 8 ) << Term1.B( 1 );
    OUT( 7 ) << Term1.A( 3 );  Drv.OUT( 7 ) << Term1.B( 3 );
    OUT( 6 ) << Term1.A( 5 );  Drv.OUT( 6 ) << Term1.B( 5 );
    OUT( 1 ) << Term1.A( 7 );  Drv.OUT( 1 ) << Term1.B( 7 );
 
    OUT( 2 ) << Term2.B( 0 );  Drv.OUT( 2 ) << Term2.A( 0 );  // >>> place resistor packs on same side as CDC319
    OUT( 3 ) << Term2.B( 1 );  Drv.OUT( 3 ) << Term2.A( 1 );
    OUT( 4 ) << Term2.B( 3 );  Drv.OUT( 4 ) << Term2.A( 3 );
    OUT( 5 ) << Term2.B( 5 );  Drv.OUT( 5 ) << Term2.A( 5 );
    OUT( 0 ) << Term2.B( 7 );  Drv.OUT( 0 ) << Term2.A( 7 );
 
    "/NC"  << Term1.A( 2 ) << Term1.A( 4 ) << Term1.A( 6 );
    "/NC"  << Term1.B( 2 ) << Term1.B( 4 ) << Term1.B( 6 );
    "/NC"  << Term2.A( 2 ) << Term2.A( 4 ) << Term2.A( 6 );
    "/NC"  << Term2.B( 2 ) << Term2.B( 4 ) << Term2.B( 6 );
  }
};
 
#endif