CBOLD IROD Example Design: std

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C⁺⁺BOLD Example Design: IROD
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// THIS FILE IS IN THE PUBLIC DOMAIN.
// IT IS PROVIDED AS IS WITHOUT WARRANTY OF ANY KIND, EITHER EXPRESSED OR IMPLIED, INCLUDING, BUT
// NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE.
 
#ifndef _STD_FPGAH_
#define _STD_FPGAH_
 
#include "xc2s150_pq208.h"
#include "jtag.h"
 
// All necessary FPGA decoupling capacitors are provided in this class.
 
class CM_STD_FPGA : public TModule {    // all FPGA wrappers on the IROD motherboard use this standard FPGA
 
// ***** dynamic members and related variables and functions ****** //
private:
  bool VrefUsed;         // OR of BankVref[]
  bool VrefByBank[ 8 ];  // one per bank, indicating if the bank's VREF is used
 
public:
  int  IO_PerBank[ 8 ];  // number of I/O's per bank, including the three VREF's per bank
 
    CM_STD_FPGA() {
      VrefUsed = false;
      for ( int b = 0; b < 8; ++ b )  VrefByBank[ b ] = false;
      IO_PerBank[ 0 ] = 13+3;   // fill in constants (this is easier than declaring IO_PerBank as static)
      IO_PerBank[ 1 ] = 15+3;
      IO_PerBank[ 2 ] = 14+3;
      IO_PerBank[ 3 ] = 14+3;
      IO_PerBank[ 4 ] = 15+3;
      IO_PerBank[ 5 ] = 12+3;
      IO_PerBank[ 6 ] = 15+3;
      IO_PerBank[ 7 ] = 15+3;
    }
 
// use UseVref( bank#, ... ) to set banks that use Vref
// up to four bank#'s can be specified in one call
// multiple calls to UseVref() are legal
  void  UseVref( int Arg0, int Arg1 = -1, int Arg2 = -1, int Arg3 = -1 ) {
    int Arg[ 4 ];     // put arguments into an array
    Arg[ 0 ] = Arg0;
    Arg[ 1 ] = Arg1;
    Arg[ 2 ] = Arg2;
    Arg[ 3 ] = Arg3;
    for ( int i = 0; i < 4; ++ i ) {
      if ( Arg[ i ] == -1 )  break;  // if default argument
      if ( Arg[ i ] > 8  ||  Arg[ i ] < 0 )
        BEGERR << "CM_STD_FPGA:UseVref(): illegal bank value of " << Arg[ i ] << ENDERR;
      VrefByBank[ Arg[ i ] ] = true;
      VrefUsed = true;
    }
  }

// the registration of these members is determined by the user's call to UseVref()
  port        Bank[ 8 ];      // I/O for each bank (less any VREF's used)
  CP_R360     PullupVREF;     // registered/wired only if VREF is used
  CP_R360     PulldownVREF;   //   "
  CP_CDC_POS  VREF_CDC;       //   "
 
// end of dynamic members //
 
 
// ***** member bundles ***** //
  CB_JTAG_CONF  JTAG_CONF;
 
// ***** member ports ***** //
  port VCC;     // 3.3V
  port VB;      // 2.5V for FPGA internal
  port GND;
 
  port GCK;        // global clock pins
 
 
// ***** member modules and parts ***** //
 
  CP_XC2S150_PQ208  Fpga;
  CP_R4_7K   INIT_Pullup;
 
  // decoupling
  enum { vc_cdc_count =  8,
         vb_cdc_count =  8,
         vc_tdc_count =  1,
         vb_tdc_count =  1 };
  CP_CDC_POS  VC_CDC[ vc_cdc_count ];    // ceramic decoupling
  CP_CDC_POS  VB_CDC[ vb_cdc_count ];
  CP_TDC_POS  VC_TDC[ vc_tdc_count ];    // tantalum decoupling
  CP_TDC_POS  VB_TDC[ vb_tdc_count ];
 
 
  virtual void Register() {
 
// bundles
    reg(  JTAG_CONF );
// ports
    reg(  VCC );
    reg(  VB  );
    reg(  GND );
 
    regb( GCK, 3, 0 );
 
// parts and modules
    reg(  Fpga );
    reg( INIT_Pullup );
 
    rega( VC_CDC, vc_cdc_count );
    rega( VB_CDC, vb_cdc_count );
    rega( VC_TDC, vc_tdc_count );
    rega( VB_TDC, vb_tdc_count );

// dynamic members
    if ( VrefUsed ) {
      reg( PullupVREF );
      reg( PulldownVREF );
      reg( VREF_CDC );
    }
    for ( int b = 0; b < 8; ++ b ) {           // register each member of Bank[]
      int IO_Count = IO_PerBank[ b ];          // the number of I/O's in each bank varies slightly
      if ( VrefByBank[ b ] )  IO_Count -= 3;   // three fewer I/O's are available if VREF is used
      regn( Bank, b );                         // register array member
      Bank[ b ].SetRange( IO_Count - 1, 0 );   // set range of member
    }
  }
 
  virtual void Connect() {
    VCC << Fpga.VCC;
    VB  << Fpga.VCCINT;
    for ( int i = 0; i < vc_cdc_count; ++ i )  VCC << VC_CDC[ i ].POS;
    for ( int i = 0; i < vb_cdc_count; ++ i )  VB  << VB_CDC[ i ].POS;
    for ( int i = 0; i < vc_tdc_count; ++ i )  VCC << VC_TDC[ i ].POS;
    for ( int i = 0; i < vb_tdc_count; ++ i )  VB  << VB_TDC[ i ].POS;
 
    wireall( GND );
 
    GCK( 0 ) << Fpga.GCK0;
    GCK( 1 ) << Fpga.GCK1;
    GCK( 2 ) << Fpga.GCK2;
    GCK( 3 ) << Fpga.GCK3;
    
    wire( JTAG_CONF, Fpga );               // works for all except DIN
    JTAG_CONF.DIN  <<  Fpga.IO153_DIN_D0;  // DIN
 
    "/NC" << Fpga.M0;  // internal pullup
    "/NC" << Fpga.M1;  // internal pullup
    GND   << Fpga.M2;
 
    "/NC" << Fpga.IO154_DOUT_BUSY;
 
    "/NC" << Fpga.DONE;       // use internal pullup >>> be sure to enable in bitgen
 
    VCC ^ INIT_Pullup ^ "INIT_N" << Fpga.IO107_INIT;
 
    "/NC"  << Fpga.PWDN_N;    // these two pins are no longer connected on the Spartan 2
    "/NC"  << Fpga.STATUS;    // Xilinx says pins should be no-connects
 
 
// ***** dynamic connections *****
    if ( VrefUsed ) {
      "VREF" << VREF_CDC.POS;
      VCC ^ PullupVREF ^ "VREF" ^ PulldownVREF ^ GND;
    }
 
    int b; int i;  bool V;
 
    i = 0;  b = 7;  V = VrefByBank[ b ];
 
    Bank[ b ]( i++ )   <<  Fpga.IO3;
    Bank[ b ]( i++ )   <<  Fpga.IO4;
    Bank[ b ]( i++ )   <<  Fpga.IO5;
    if ( V ) { "VREF"  <<  Fpga.IO6_VREF; } else {
    Bank[ b ]( i++ )   <<  Fpga.IO6_VREF; }
    Bank[ b ]( i++ )   <<  Fpga.IO7;
    Bank[ b ]( i++ )   <<  Fpga.IO8;
    if ( V ) { "VREF"  <<  Fpga.IO9_VREF; } else {
    Bank[ b ]( i++ )   <<  Fpga.IO9_VREF; }
    Bank[ b ]( i++ )   <<  Fpga.IO10;
    Bank[ b ]( i++ )   <<  Fpga.IO14;
    Bank[ b ]( i++ )   <<  Fpga.IO15;
    Bank[ b ]( i++ )   <<  Fpga.IO16;
    Bank[ b ]( i++ )   <<  Fpga.IO17;
    Bank[ b ]( i++ )   <<  Fpga.IO18;
    if ( V ) { "VREF"  <<  Fpga.IO20_VREF; } else {
    Bank[ b ]( i++ )   <<  Fpga.IO20_VREF; }
    Bank[ b ]( i++ )   <<  Fpga.IO21;
    Bank[ b ]( i++ )   <<  Fpga.IO22;
    Bank[ b ]( i++ )   <<  Fpga.IO23;
    Bank[ b ]( i++ )   <<  Fpga.IO24_IRDY;

    if ( i + (V ? 3 : 0)   !=  IO_PerBank[ b ] )
      BEGERR << "CM_STD_FPGA:Connect(): IO_PerBank mismatch, attempt to connect " << i << " pins to bank " << b << ENDERR;
 
    i = 0;  b = 6;  V = VrefByBank[ b ];
 
    Bank[ b ]( i++ )   <<  Fpga.IO27_TRDY;
    Bank[ b ]( i++ )   <<  Fpga.IO29;
    Bank[ b ]( i++ )   <<  Fpga.IO30;
    if ( V ) { "VREF"  <<  Fpga.IO31_VREF; } else {
    Bank[ b ]( i++ )   <<  Fpga.IO31_VREF; }
    Bank[ b ]( i++ )   <<  Fpga.IO33;
    Bank[ b ]( i++ )   <<  Fpga.IO34;
    Bank[ b ]( i++ )   <<  Fpga.IO35;
    Bank[ b ]( i++ )   <<  Fpga.IO36;
    Bank[ b ]( i++ )   <<  Fpga.IO37;
    Bank[ b ]( i++ )   <<  Fpga.IO41;
    if ( V ) { "VREF"  <<  Fpga.IO42_VREF; } else {
    Bank[ b ]( i++ )   <<  Fpga.IO42_VREF; }
    Bank[ b ]( i++ )   <<  Fpga.IO43;
    Bank[ b ]( i++ )   <<  Fpga.IO44;
    if ( V ) { "VREF"  <<  Fpga.IO45_VREF; } else {
    Bank[ b ]( i++ )   <<  Fpga.IO45_VREF; }
    Bank[ b ]( i++ )   <<  Fpga.IO46;
    Bank[ b ]( i++ )   <<  Fpga.IO47;
    Bank[ b ]( i++ )   <<  Fpga.IO48;
    Bank[ b ]( i++ )   <<  Fpga.IO49;
 
    if ( i + (V ? 3 : 0)   !=  IO_PerBank[ b ] )
      BEGERR << "CM_STD_FPGA:Connect(): IO_PerBank mismatch, attempt to connect " << i << " pins to bank " << b << ENDERR;
 
    i = 0;  b = 5;  V = VrefByBank[ b ];
 
    Bank[ b ]( i++ )   <<  Fpga.IO57;
    Bank[ b ]( i++ )   <<  Fpga.IO58;
    if ( V ) { "VREF"  <<  Fpga.IO59_VREF; } else {
    Bank[ b ]( i++ )   <<  Fpga.IO59_VREF; }
    Bank[ b ]( i++ )   <<  Fpga.IO60;
    Bank[ b ]( i++ )   <<  Fpga.IO61;
    if ( V ) { "VREF"  <<  Fpga.IO62_VREF; } else {
    Bank[ b ]( i++ )   <<  Fpga.IO62_VREF; }
    Bank[ b ]( i++ )   <<  Fpga.IO63;
    Bank[ b ]( i++ )   <<  Fpga.IO67;
    Bank[ b ]( i++ )   <<  Fpga.IO68;
    Bank[ b ]( i++ )   <<  Fpga.IO69;
    Bank[ b ]( i++ )   <<  Fpga.IO70;
    Bank[ b ]( i++ )   <<  Fpga.IO71;
    if ( V ) { "VREF"  <<  Fpga.IO73_VREF; } else {
    Bank[ b ]( i++ )   <<  Fpga.IO73_VREF; }
    Bank[ b ]( i++ )   <<  Fpga.IO74;
    Bank[ b ]( i++ )   <<  Fpga.IO75;
 
    if ( i + (V ? 3 : 0)   !=  IO_PerBank[ b ] )
      BEGERR << "CM_STD_FPGA:Connect(): IO_PerBank mismatch, attempt to connect " << i << " pins to bank " << b << ENDERR;
 
    i = 0;  b = 4;  V = VrefByBank[ b ];
 
    Bank[ b ]( i++ )   <<  Fpga.IO81;
    Bank[ b ]( i++ )   <<  Fpga.IO82;
    Bank[ b ]( i++ )   <<  Fpga.IO83;
    if ( V ) { "VREF"  <<  Fpga.IO84_VREF; } else {
    Bank[ b ]( i++ )   <<  Fpga.IO84_VREF; }
    Bank[ b ]( i++ )   <<  Fpga.IO86;
    Bank[ b ]( i++ )   <<  Fpga.IO87;
    Bank[ b ]( i++ )   <<  Fpga.IO88;
    Bank[ b ]( i++ )   <<  Fpga.IO89;
    Bank[ b ]( i++ )   <<  Fpga.IO90;
    Bank[ b ]( i++ )   <<  Fpga.IO94;
    if ( V ) { "VREF"  <<  Fpga.IO95_VREF; } else {
    Bank[ b ]( i++ )   <<  Fpga.IO95_VREF; }
    Bank[ b ]( i++ )   <<  Fpga.IO96;
    Bank[ b ]( i++ )   <<  Fpga.IO97;
    if ( V ) { "VREF"  <<  Fpga.IO98_VREF; } else {
    Bank[ b ]( i++ )   <<  Fpga.IO98_VREF; }
    Bank[ b ]( i++ )   <<  Fpga.IO99;
    Bank[ b ]( i++ )   <<  Fpga.IO100;
    Bank[ b ]( i++ )   <<  Fpga.IO101;
    Bank[ b ]( i++ )   <<  Fpga.IO102;
 
    if ( i + (V ? 3 : 0)   !=  IO_PerBank[ b ] )
      BEGERR << "CM_STD_FPGA:Connect(): IO_PerBank mismatch, attempt to connect " << i << " pins to bank " << b << ENDERR;
 
    i = 0;  b = 3;  V = VrefByBank[ b ];
 
//  Bank[ b ]( i++ )   <<  Fpga.IO107_INIT;
    Bank[ b ]( i++ )   <<  Fpga.IO108_D7;
    Bank[ b ]( i++ )   <<  Fpga.IO109;
    Bank[ b ]( i++ )   <<  Fpga.IO110;
    if ( V ) { "VREF"  <<  Fpga.IO111_VREF; } else {
    Bank[ b ]( i++ )   <<  Fpga.IO111_VREF; }
    Bank[ b ]( i++ )   <<  Fpga.IO112;
    Bank[ b ]( i++ )   <<  Fpga.IO113;
    if ( V ) { "VREF"  <<  Fpga.IO114_VREF; } else {
    Bank[ b ]( i++ )   <<  Fpga.IO114_VREF; }
    Bank[ b ]( i++ )   <<  Fpga.IO115_D6;
    Bank[ b ]( i++ )   <<  Fpga.IO119_D5;
    Bank[ b ]( i++ )   <<  Fpga.IO120;
    Bank[ b ]( i++ )   <<  Fpga.IO121;
    Bank[ b ]( i++ )   <<  Fpga.IO122;
    Bank[ b ]( i++ )   <<  Fpga.IO123;
    if ( V ) { "VREF"  <<  Fpga.IO125_VREF; } else {
    Bank[ b ]( i++ )   <<  Fpga.IO125_VREF; }
    Bank[ b ]( i++ )   <<  Fpga.IO126_D4;
    Bank[ b ]( i++ )   <<  Fpga.IO127;
    Bank[ b ]( i++ )   <<  Fpga.IO129_TRDY;
 
    if ( i + (V ? 3 : 0)   !=  IO_PerBank[ b ] )
      BEGERR << "CM_STD_FPGA:Connect(): IO_PerBank mismatch, attempt to connect " << i << " pins to bank " << b << ENDERR;
 
    i = 0;  b = 2;  V = VrefByBank[ b ];
 
    Bank[ b ]( i++ )   <<  Fpga.IO132_IRDY;
    Bank[ b ]( i++ )   <<  Fpga.IO133;
    Bank[ b ]( i++ )   <<  Fpga.IO134;
    Bank[ b ]( i++ )   <<  Fpga.IO135_D3;
    if ( V ) { "VREF"  <<  Fpga.IO136_VREF; } else {
    Bank[ b ]( i++ )   <<  Fpga.IO136_VREF; }
    Bank[ b ]( i++ )   <<  Fpga.IO138;
    Bank[ b ]( i++ )   <<  Fpga.IO139;
    Bank[ b ]( i++ )   <<  Fpga.IO140;
    Bank[ b ]( i++ )   <<  Fpga.IO141;
    Bank[ b ]( i++ )   <<  Fpga.IO142_D2;
    Bank[ b ]( i++ )   <<  Fpga.IO146_D1;
    if ( V ) { "VREF"  <<  Fpga.IO147_VREF; } else {
    Bank[ b ]( i++ )   <<  Fpga.IO147_VREF; }
    Bank[ b ]( i++ )   <<  Fpga.IO148;
    Bank[ b ]( i++ )   <<  Fpga.IO149;
    if ( V ) { "VREF"  <<  Fpga.IO150_VREF; } else {
    Bank[ b ]( i++ )   <<  Fpga.IO150_VREF; }
    Bank[ b ]( i++ )   <<  Fpga.IO151;
    Bank[ b ]( i++ )   <<  Fpga.IO152;
//  Bank[ b ]( i++ )   <<  Fpga.IO153_DIN_D0;
//  Bank[ b ]( i++ )   <<  Fpga.IO154_DOUT_BUSY;
 
    if ( i + (V ? 3 : 0)   !=  IO_PerBank[ b ] )
      BEGERR << "CM_STD_FPGA:Connect(): IO_PerBank mismatch, attempt to connect " << i << " pins to bank " << b << ENDERR;
 
    i = 0;  b = 1;  V = VrefByBank[ b ];
 
    Bank[ b ]( i++ )   <<  Fpga.IO160_CS_N;
    Bank[ b ]( i++ )   <<  Fpga.IO161_WRITE_N;
    Bank[ b ]( i++ )   <<  Fpga.IO162;
    Bank[ b ]( i++ )   <<  Fpga.IO163;
    if ( V ) { "VREF"  <<  Fpga.IO164_VREF; } else {
    Bank[ b ]( i++ )   <<  Fpga.IO164_VREF; }
    Bank[ b ]( i++ )   <<  Fpga.IO165;
    Bank[ b ]( i++ )   <<  Fpga.IO166;
    if ( V ) { "VREF"  <<  Fpga.IO167_VREF; } else {
    Bank[ b ]( i++ )   <<  Fpga.IO167_VREF; }
    Bank[ b ]( i++ )   <<  Fpga.IO168;
    Bank[ b ]( i++ )   <<  Fpga.IO172;
    Bank[ b ]( i++ )   <<  Fpga.IO173;
    Bank[ b ]( i++ )   <<  Fpga.IO174;
    Bank[ b ]( i++ )   <<  Fpga.IO175;
    Bank[ b ]( i++ )   <<  Fpga.IO176;
    if ( V ) { "VREF"  <<  Fpga.IO178_VREF; } else {
    Bank[ b ]( i++ )   <<  Fpga.IO178_VREF; }
    Bank[ b ]( i++ )   <<  Fpga.IO179;
    Bank[ b ]( i++ )   <<  Fpga.IO180;
    Bank[ b ]( i++ )   <<  Fpga.IO181;
 
    if ( i + (V ? 3 : 0)   !=  IO_PerBank[ b ] )
      BEGERR << "CM_STD_FPGA:Connect(): IO_PerBank mismatch, attempt to connect " << i << " pins to bank " << b << ENDERR;
 
    i = 0;  b = 0;  V = VrefByBank[ b ];
 
    Bank[ b ]( i++ )   <<  Fpga.IO187;
    Bank[ b ]( i++ )   <<  Fpga.IO188;
    if ( V ) { "VREF"  <<  Fpga.IO189_VREF; } else {
    Bank[ b ]( i++ )   <<  Fpga.IO189_VREF; }
    Bank[ b ]( i++ )   <<  Fpga.IO191;
    Bank[ b ]( i++ )   <<  Fpga.IO192;
    Bank[ b ]( i++ )   <<  Fpga.IO193;
    Bank[ b ]( i++ )   <<  Fpga.IO194;
    Bank[ b ]( i++ )   <<  Fpga.IO195;
    Bank[ b ]( i++ )   <<  Fpga.IO199;
    if ( V ) { "VREF"  <<  Fpga.IO200_VREF; } else {
    Bank[ b ]( i++ )   <<  Fpga.IO200_VREF; }
    Bank[ b ]( i++ )   <<  Fpga.IO201;
    Bank[ b ]( i++ )   <<  Fpga.IO202;
    if ( V ) { "VREF"  <<  Fpga.IO203_VREF; } else {
    Bank[ b ]( i++ )   <<  Fpga.IO203_VREF; }
    Bank[ b ]( i++ )   <<  Fpga.IO204;
    Bank[ b ]( i++ )   <<  Fpga.IO205;
    Bank[ b ]( i++ )   <<  Fpga.IO206;
 
    if ( i + (V ? 3 : 0)   !=  IO_PerBank[ b ] )
      BEGERR << "CM_STD_FPGA:Connect(): IO_PerBank mismatch, attempt to connect " << i << " pins to bank " << b << ENDERR;
 
  }
};
 
#endif
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