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C++BOLD Example Design: TTM

// THIS FILE IS IN THE PUBLIC DOMAIN.
// IT IS PROVIDED AS IS WITHOUT WARRANTY OF ANY KIND, EITHER EXPRESSED OR IMPLIED, INCLUDING, BUT
// NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE.
 
#ifndef _TTM_RxTxH_
#define _TTM_RxTxH_
 
#include "hdmp.h"   // Agilent HDMP parts
 
// The classes in this file encapsulate the Agilent HDMP serializer and deserializer in a way appropriate to the Test Transition Module.
// Decoupling and other miscellaneous components are provided.
 
 
// *** Tx *** //
 
class CB_Tx_Bussed : public TBundle {  // bussed Tx connections from backplane
public:
  port TX;          // from backplane
  port TXFLAG;
  port TXDATA;
  port TXCNTL;
  port TXFLGENB;
  port TXESMPXENB;    // pin name changed from ESMPXENB so that TX and RX ESMPXENB are more easily bussed separately
  port TXDIV0;
  port TXDIV1;
 
  virtual void Register() {
    regb( TX, 15, 0  );
    reg(  TXFLAG     );
    reg(  TXDATA     );
    reg(  TXCNTL     );
    reg(  TXFLGENB   );
    reg(  TXESMPXENB );
    reg(  TXDIV0     );
    reg(  TXDIV1     );
  }
};
 
class CB_Tx_PtToPt : public TBundle {  // point-to-point connections to backplane
public:
  port TXLOCKED;     // output to backplane (optional), pin name changed from LOCKED for consistency with other TX and RX port names
 
  virtual void Register() {
    reg(  TXLOCKED    );
  }
};
 
 
class CB_Tx_Back : public TBundle {  // Tx connections to/from backplane
public:
  CB_Tx_Bussed  Bussed;
  CB_Tx_PtToPt  PtToPt;
  virtual void Register() {
    reg( Bussed );
    reg( PtToPt );
  }
};
 
 
 
class CM_Wrapped1032 : public TModule {  // wrapper for HDMP_1032 serializer (transmitter)
 
public:
 
// ***** member bundles ***** //
  CB_Tx_Back   Back;     // connections to backplane subsystem
 
// ***** member ports ***** //
  port VCC;     // 3.3V
  port GND;
 
  port TXCLK;
 
  port HSOUT_N;
  port HSOUT_P;
 
 
// ***** member parts ***** //
 
  CP_HDMP_1032  Tx;
  CP_C100NF     FilterCap;
 
  // decoupling and power filtering
                                           // >>> each HDMP-1032 VCC pin gets a decoupling capacitor
  enum { vc_cdc_count =  5                 // >>> for VCC
                        +2                 // >>> for VCC_TTL
                        +1 };              // >>> for VCC_HS
 
  CP_CDC_POS    VC_CDC[ vc_cdc_count ];    // ceramic decoupling
  CP_CDC_POS    VCA1_CDC;                  // additional CDC's for VCC_An (VCC via ferrite)
  CP_CDC_POS    VCA2_CDC;
  CP_FERRITE120 VCA1_Ferrite;              // ferrites for VCC_An
  CP_FERRITE120 VCA2_Ferrite;
 
  virtual void Register() {
// bundles
    reg( Back );
 
// ports
    reg(  VCC );
    reg(  GND );
 
    reg(  TXCLK    );
    reg(  HSOUT_N  );
    reg(  HSOUT_P  );
 
// parts
    reg(  Tx );
    reg(  FilterCap );
 
    rega( VC_CDC, vc_cdc_count );
 
    reg(  VCA1_CDC );
    reg(  VCA2_CDC );
    reg(  VCA1_Ferrite );
    reg(  VCA2_Ferrite );
  }
 
  virtual void Connect() {
 
    wire( Back, Tx );                         // Tx pins connected directly to module bundles/ports
    Back.Bussed.TXESMPXENB  <<  Tx.ESMPXENB;  // connected to bundle, but with name change
    Back.PtToPt.TXLOCKED    <<  Tx.LOCKED;    // connected to bundle, but with name change
 
    wire( TXCLK    );
 
    wire( HSOUT_N  );
    wire( HSOUT_P  );
 
 
    wireall( GND );
    GND << Tx.GND_TTL;
    GND << Tx.GND_HS;
    GND << Tx.GND_A1;
    GND << Tx.GND_A2;
 
    VCC << Tx.VCC;
    VCC << Tx.VCC_TTL;
    VCC << Tx.VCC_HS;
 
    for ( int i = 0; i < vc_cdc_count; ++ i )  VCC << VC_CDC[ i ].POS;
 
    VCC  ^ VCA1_Ferrite ^  "AVCC1" << Tx.VCC_A1 << VCA1_CDC.POS;   // analog VCC via ferrite
    VCC  ^ VCA2_Ferrite ^  "AVCC2" << Tx.VCC_A2 << VCA2_CDC.POS;
 
    Tx.TXCAP0 << "CAP0" ^ FilterCap ^ "CAP1" << Tx.TXCAP1;     // PLL filter
 
 
    GND << Tx.TCLKENB;   // use the PLL as the serial clock, not TXCLK
 
    "/NC" << Tx.NC;
  }
};
 
 
// *** Rx *** //
 
class CB_Rx_Bussed : public TBundle {  // bussed Rx connections from backplane
public:
  port RXFLGENB;
  port RXESMPXENB;    // pin name changed from ESMPXENB so that TX and RX ESMPXENB are more easily bussed separately
  port RXDIV0;
  port RXDIV1;
 
  virtual void Register() {
    reg(  RXFLGENB  );
    reg(  RXESMPXENB  );
    reg(  RXDIV0    );
    reg(  RXDIV1    );
  }
};
 
class CB_Rx_PtToPt : public TBundle {  // point-to-point connections to backplane
public:
  port RX;
  port RXFLAG;
  port RXDATA;
  port RXERROR;
  port RXREADY;
 
  virtual void Register() {
    regb( RX, 15, 0 );
    reg(  RXFLAG    );
    reg(  RXDATA    );
    reg(  RXERROR   );
    reg(  RXREADY   );
  }
};
 
 
class CB_Rx_Back : public TBundle {  // Rx connections to/from backplane
public:
  CB_Rx_Bussed  Bussed;
  CB_Rx_PtToPt  PtToPt;
  virtual void Register() {
    reg( Bussed );
    reg( PtToPt );
  }
};
 
 
 
class CM_Wrapped1034 : public TModule {  // wrapper for HDMP_1034 serializer (transmitter)
 
public:
 
// ***** member bundles ***** //
  CB_Rx_Back   Back;     // connections to backplane subsystem
 
// ***** member ports ***** //
  port VCC;     // 3.3V
  port GND;
 
  port REFCLK;
 
  port HSIN_N;
  port HSIN_P;
 
 
// ***** member parts ***** //
 
  CP_HDMP_1034    Rx;
  CP_C100NF       FilterCap;
                                           // series termination, 56 ohm isolated resistor pack
                                           // <<< place all STerm's near HDMP-1034's
  CP_EXB2HV560JV  STermL;                  // for RX LSB
  CP_EXB2HV560JV  STermH;                  // for RX MSB
  CP_EXB2HV560JV  STermV;                  // for various RX signals
 
 
  // decoupling and power filtering
                                           // >>> each HDMP-1034 VCC pin gets a decoupling capacitor
  enum { vc_cdc_count =  3                 // >>> for VCC
                        +5                 // >>> for VCC_TTL
                        +1 };              // >>> for VCC_HS
 
  CP_CDC_POS    VC_CDC[ vc_cdc_count ];    // ceramic decoupling
  CP_CDC_POS    VCA_CDC;                   // additional CDC for VCC_A (VCC via ferrite)
  CP_FERRITE120 VCA_Ferrite;               // ferrite for VCC_A
 
  virtual void Register() {
// bundles
    reg( Back );
 
// ports
    reg(  VCC );
    reg(  GND );
 
    reg(  REFCLK    );
    reg(  HSIN_N  );
    reg(  HSIN_P  );
 
// parts
    reg(  Rx );
    reg(  FilterCap );
    reg(  STermL );
    reg(  STermH );
    reg(  STermV );
 
    rega( VC_CDC, vc_cdc_count );
 
    reg(  VCA_CDC );
    reg(  VCA_Ferrite );
  }
 
  virtual void Connect() {
 
    wire( Back.Bussed, Rx );                  // Rx pins connected directly to module bundles/ports
    Back.Bussed.RXESMPXENB  <<  Rx.ESMPXENB;  // connected to bundle, but with name change
 
    // point-to-point connections via series terminator arrays
 
    "LOC_RX" << Rx.RX;    // pre-terminator RX
    Back.PtToPt.RX(  7, 0)  <<  STermL.B;       STermL.A      <<  Rx.RX(  7, 0 );   // arranged for optimal layout
    Back.PtToPt.RX( 15, 8)  <<  STermH.B;       STermH.A      <<  Rx.RX( 15, 8 );
 
    int i = 0;
    Back.PtToPt.RXREADY     <<  STermV.B( i );  STermV.A( i++ ) <<  Rx.RXREADY  <<  "LOC_RXREADY";
    "/NC"                   <<  STermV.B( i );  STermV.A( i++ ) <<  "/NC";
    Back.PtToPt.RXERROR     <<  STermV.B( i );  STermV.A( i++ ) <<  Rx.RXERROR  <<  "LOC_RXERROR";
    "/NC"                   <<  STermV.B( i );  STermV.A( i++ ) <<  "/NC";
    Back.PtToPt.RXFLAG      <<  STermV.B( i );  STermV.A( i++ ) <<  Rx.RXFLAG   <<  "LOC_RXFLAG";
    "/NC"                   <<  STermV.B( i );  STermV.A( i++ ) <<  "/NC";
    Back.PtToPt.RXDATA      <<  STermV.B( i );  STermV.A( i++ ) <<  Rx.RXDATA   <<  "LOC_RXDATA";
    "/NC"                   <<  STermV.B( i );  STermV.A( i++ ) <<  "/NC";
 
 
    wire( REFCLK   );
 
    wire( HSIN_N  );
    wire( HSIN_P  );
 
 
    wireall( GND );
    GND << Rx.GND_TTL;
    GND << Rx.GND_HS;
    GND << Rx.GND_A;
 
    VCC << Rx.VCC;
    VCC << Rx.VCC_TTL;
    VCC << Rx.VCC_HS;
 
    for ( int i = 0; i < vc_cdc_count; ++ i )  VCC << VC_CDC[ i ].POS;
 
    VCC  ^ VCA_Ferrite ^  "AVCC" << Rx.VCC_A << VCA_CDC.POS;   // analog VCC via ferrite
 
    Rx.RXCAP0 << "CAP0" ^ FilterCap ^ "CAP1" << Rx.RXCAP1;     // PLL filter
 
 
    VCC   << Rx.TSTCLK;    // test pins with connections per data sheet
    VCC   << Rx.RESET_N;
    GND   << Rx.WSYNCDSB;
 
 
    GND   << Rx.PASSENB;   // PASS pins with connections per data sheet (PASS not used)
    "/NC" << Rx.SRQIN;
    "/NC" << Rx.SRQOUT;
    "/NC" << Rx.SHFIN;
    "/NC" << Rx.SHFOUT;
    "/NC" << Rx.RXDSLIP;
 
    "/NC" << Rx.RXCLK0;  // recovered clock outputs, not used
    "/NC" << Rx.RXCLK1;
    "/NC" << Rx.RXCNTL;  // CNTL word indicator, not used
    "/NC" << Rx.NC;
  }
};
 
#endif