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C++BOLD Example Design: IROD

// THIS FILE IS IN THE PUBLIC DOMAIN.
// IT IS PROVIDED AS IS WITHOUT WARRANTY OF ANY KIND, EITHER EXPRESSED OR IMPLIED, INCLUDING, BUT
// NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE.
 
#ifndef _InterconnectH_
#define _InterconnectH_
 
#include "jtag.h"
#include "clock_generation.h"
#include "ttc_fpga.h"
#include "bpi_fpga.h"
 
// The Interconnect subsystem routes signals between the following:
//   HPU
//   DPU's
//   generic backplane pins
 
// All necessary decoupling capacitors are already included.
 
 
// CB_Front_IC: interface between FrontPanel and Interconnect
class CB_Front_IC : public TBundle {
public:
  port TTC0P;
  port TTC0N;
  port TTC1P;
  port TTC1N;
  virtual void Register() {
    reg( TTC0P );
    reg( TTC0N );
    reg( TTC1P );
    reg( TTC1N );
  }
};
 
 
// CB_Half_IC: interface between HalfROD and Interconnect
class CB_Half_IC : public TBundle {
public:
  port IC_BUS;                        // bus connections to all DPU's in half (from TTC FPGA)
  port IC_DPU[ DPU_HalfCount ];       // generic DPU connections to individual DPU's
 
  virtual void Register() {
    regb(  IC_BUS, 5, 0 );                    // one bus per half, 6 wires
    regab( IC_DPU, DPU_HalfCount, 24, 0 );    // one bus per DPU, 25 wires per bus
  }
};
 
 
// CB_Back_IC: interface between Backplane and Interconnect
class CB_Back_IC : public TBundle {
public:
                     // TTC FPGA generic connections to backplane
  port TG;           // for ATLAS, TG[7:0] will be connected to signals TTC7-TTC0, which are a backplane bus from the TIM
  port TMP_N;        // transition module present indicator
 
                     // BPI FPGA generic connections to backplane
  port BG_A[ 6 ];    // A and B are suggestions only
  port BG_B[ 6 ];    // FPGA pins for these ports are located reasonably with respect to corresponding DPU FPGA pins
 
  virtual void Register() {
    regb( TG,       15, 0 );
    reg(   TMP_N );
    regab( BG_A, 6, 15, 0 );    // one A bus per BPI FPGA, 16 wires per bus
    regab( BG_B, 6, 15, 0 );    // one B bus per BPI FPGA, 16 wires per bus
  }
};
 
 
// CB_Host_IC: interface between Host and Interconnect
class CB_Host_IC : public TBundle {
public:
  port HG;         // HPU <--> TTC_FPGA generic connections
 
                   // Host asynchronous EMIF connections (via FPGA, transceiver, PLD, etc.)
  port D;          // data
  port A;          // address
  port BPI_STB_N;  // one strobe per BPI FPGA
  port TTC_STB_N;  // one strobe for the TTC FPGA
  port WR_N;       // one read/write* signal to all FPGA's
 
  virtual void Register() {
    regb(    HG,  7, 0 );
    regb(     D, 15, 0 );
    regb(     A,  3, 0 );
    regb( BPI_STB_N,  5, 0 );
    reg(  TTC_STB_N    );
    reg(   WR_N );
  }
};
 
 
class CM_Interconnect : public TModule {    // Interconnect Subsystem
public:
// ***** member bundles ***** //
  CB_Back_IC   BK;    // interface to Backplane
  CB_IC_CG     CG;    // interface to ClockGeneration
  CB_Front_IC  FP;    // interface to FrontPanel
  CB_Half_IC   A;     // interface to Half's
  CB_Half_IC   B;
  CB_Host_IC   HO;    // interface to Host
  CB_IC_JT     JT;    // interface to JTAG
 
// ***** member ports ***** //
  port MB_VCC;       // 3.3V
  port MB_VB;        // 2.5V for FPGA internal
  port GND;
 
 
// ***** member modules and parts ***** //
  CM_BPI_FPGA        BPI_FPGA[ 6 ];   // register these first so that reference designators are U0-U5
  CM_TTC_FPGA        TTC_FPGA;
  CP_SN65LVDS9637B  Rcv_FP_TTC;      // dual wide-common-mode differential receiver for FrontPanel inputs
  CP_R30            STerm_FP_TTC0;   // series terminators for receiver outputs
  CP_R30            STerm_FP_TTC1;
  CP_R4_7K          PullupTMP_N;     // pullup for transition module present indicator (grounded on TM)
 
  CP_CDC_POS        Rcv_FP_VC_CDC;   // ceramic decoupling for receiver
 
 
 
  virtual void Register() {
// bundles
    reg( BK );
    reg( CG );
    reg( FP );
    reg( A  );
    reg( B  );
    reg( HO );
    reg( JT );
// ports
    reg( MB_VCC );
    reg( MB_VB  );
    reg( GND );
 
// parts and modules
    rega( BPI_FPGA, 6 );
    reg(  TTC_FPGA );
    reg(  Rcv_FP_TTC );
    reg(  STerm_FP_TTC0 );
    reg(  STerm_FP_TTC1 );
    reg(  PullupTMP_N   );
    
    reg(  Rcv_FP_VC_CDC );
  }
 
  virtual void Connect() {
    wireall( MB_VCC, "VCC" );
    wireall( MB_VB,  "VB"  );
    wireall( GND );
    MB_VCC  <<  Rcv_FP_VC_CDC.POS;
 
// JTAG
    wire( JT.TTC_FPGA, TTC_FPGA.JTAG_CONF );
    for ( int i = 0; i < 6; ++ i ) {
      wire( JT.BPI_FPGA[ i ], BPI_FPGA[ i ].JTAG_CONF );
    }
 
// clocks (see also STB_N below)
    for ( int i = 0; i < 6; i += 2 ) {                 // clocks to BPI FPGA pairs
      CG.RCLK( i >> 1 )  <<  BPI_FPGA[ i     ].RCLK
                         <<  BPI_FPGA[ i + 1 ].RCLK;
      CG.SCLK( i >> 1 )  <<  BPI_FPGA[ i     ].SCLK
                         <<  BPI_FPGA[ i + 1 ].SCLK;
      CG.TCLK( i >> 1 )  <<  BPI_FPGA[ i     ].TCLK
                         <<  BPI_FPGA[ i + 1 ].TCLK;
    }
    TTC_FPGA.RCLK  << CG.RCLK( 3 );
    TTC_FPGA.SCLK  << CG.SCLK( 3 );
    TTC_FPGA.TCLK  << CG.TCLK( 3 );
 
// front panel general-purpose signals via differential receiver and series terminator to TTC FPGA
    Rcv_FP_TTC.IN_P1  << FP.TTC0P;    // user is responsible for terminators, e.g., on end of user's ribbon cable
    Rcv_FP_TTC.IN_N1  << FP.TTC0N;
    Rcv_FP_TTC.IN_P2  << FP.TTC1P;
    Rcv_FP_TTC.IN_N2  << FP.TTC1N;
 
    Rcv_FP_TTC.OUT1 << "LOC_TTC0"  ^ STerm_FP_TTC0 ^  "TTC0" << TTC_FPGA.FP_TTC( 0 );
    Rcv_FP_TTC.OUT2 << "LOC_TTC1"  ^ STerm_FP_TTC1 ^  "TTC1" << TTC_FPGA.FP_TTC( 1 );
 
 
// connections to Host
    TTC_FPGA.HG     << HO.HG;
 
    TTC_FPGA.D      << HO.D;
    TTC_FPGA.A      << HO.A;
    TTC_FPGA.WR_N   << HO.WR_N;
    TTC_FPGA.STB_N  << HO.TTC_STB_N;
 
    for ( int i = 0; i < 6; ++ i ) {
      BPI_FPGA[ i ].D      << HO.D( 3, 0 );
      BPI_FPGA[ i ].A      << HO.A;
      BPI_FPGA[ i ].WR_N   << HO.WR_N;
      BPI_FPGA[ i ].STB_N  << HO.BPI_STB_N( i );
    }
 
 
    // TTC_FPGA <--> all BPI_FPGA's connections
    conn( "TTC_TO_BPI", TTC_FPGA.BPI, 6 );   // for readable net names
    for ( int i = 0; i < 6; ++ i ) {
      TTC_FPGA.BPI[ i ] << BPI_FPGA[ i ].AUX( 7, 0 );
    }
 
    // TTC_FPGA <--> central BPI_FPGA--additional connections
    conn( "TTC_TO_CEN", TTC_FPGA.CEN, 2 );   // for readable net names
    TTC_FPGA.CEN[ 0 ] << BPI_FPGA[ 1 ].AUX( 11, 8 );
    TTC_FPGA.CEN[ 1 ] << BPI_FPGA[ 4 ].AUX( 11, 8 );
 
 
    // BPI FPGA's <--> DPU pt-to-pt connections
    for ( int i = 0; i < 6; ++ i ) {
      A.IC_DPU[ i ] << BPI_FPGA[ i ].DPU_A( 24, 0 );
      B.IC_DPU[ i ] << BPI_FPGA[ i ].DPU_B( 24, 0 );
    }
    // TTC FPGA <--> DPU bussed connections
    A.IC_BUS << TTC_FPGA.BUS_A;
    B.IC_BUS << TTC_FPGA.BUS_B;
 
    TTC_FPGA.TMP_N  <<  BK.TMP_N  ^ PullupTMP_N ^  MB_VCC;  // transition module present indicator, grounded on TM
 
    // FPGA <--> Backplane generic connections
    TTC_FPGA.TG    << BK.TG;
 
    for ( int i = 0; i < 6; ++ i ) {
      BPI_FPGA[ i ].BG_A << BK.BG_A[ i ];
      BPI_FPGA[ i ].BG_B << BK.BG_B[ i ];
    }
 
 // shared connections and cross connections between BPI FPGA's:
 // central BG_A and BG_B are shared with adjacent FPGA's AUX(23, 8)
 // central AUX(23, 12) connect to CROSS's of non-central FPGA's of opposite half
 // central CROSS's are connected together
 
    BPI_FPGA[ 1 ].BG_A << BPI_FPGA[ 0 ].AUX( 23, 8 );    // shared connections
    BPI_FPGA[ 1 ].BG_B << BPI_FPGA[ 2 ].AUX( 23, 8 );
    BPI_FPGA[ 4 ].BG_A << BPI_FPGA[ 3 ].AUX( 23, 8 );
    BPI_FPGA[ 4 ].BG_B << BPI_FPGA[ 5 ].AUX( 23, 8 );
 
    "CROSS_1_3_" << BPI_FPGA[ 3 ].CROSS << BPI_FPGA[ 1 ].AUX( 17, 12 );
    "CROSS_1_5_" << BPI_FPGA[ 5 ].CROSS << BPI_FPGA[ 1 ].AUX( 23, 18 );
    "CROSS_4_0_" << BPI_FPGA[ 0 ].CROSS << BPI_FPGA[ 4 ].AUX( 17, 12 );
    "CROSS_4_2_" << BPI_FPGA[ 2 ].CROSS << BPI_FPGA[ 4 ].AUX( 23, 18 );
 
    "CROSS_1_4_" << BPI_FPGA[ 1 ].CROSS << BPI_FPGA[ 4 ].CROSS;
  }
};
 
#endif