CBOLD IROD Example Design: host.h

Coolquest, Inc.
C⁺⁺BOLD Example Design: IROD
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// THIS FILE IS IN THE PUBLIC DOMAIN.
// IT IS PROVIDED AS IS WITHOUT WARRANTY OF ANY KIND, EITHER EXPRESSED OR IMPLIED, INCLUDING, BUT
// NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE.
 
#ifndef _HostH_
#define _HostH_
 
#include "sn74lvth162245.h" //Include tranceivers
#include "host_pld.h"        //Host PLD Wrapper
#include "gpu.h"
#include "vme_interface.h"  //For Host<->VME Bundle
#include "dallas.h"         // for serial number chip
 
class CM_Host : public TModule {    // Host Subsystem
public:
// ***** member bundles ***** //
  CB_Host_BK         BK;     // interface to Backplane
  CB_Host_CG         CG;     // interface to ClockGeneration
  CB_Host_DC         DC;     // interface to DPU_Control
  CB_Host_DX         DX;     // interface to DataExchange
  CB_Host_IC         IC;     // interface to Interconnect
  CB_Host_JT         JT;     // interface to JTAG
  CB_Host_VME        VME;    // interface to VME
  CB_MeasureControl  MeasCtrl;    // power (voltage and current) measurement is under Host control
 
// ***** member ports ***** //
  port MB_VCC;        // 3.3V
  port DSP_VCC;       // 3.3V for HPU
  port DSP_VB;        // 2.5V for HPU FPGA's
  port DSP_VA;        // VCORE for HPU DSP
 
  port GND;
 
                    // convenience ports, for convenient wiring below and net naming at the root level
  port BA;          // buffered address bus
  port BDF;         // buffered data busses
  port BDG;
  port BDH;
 
 
// ***** member modules and parts ***** //
  CM_HPU                 HPU;               // Host Processing Unit (DSP module)
  CP_SN74CBTLV1G125DBV  SwitchJTAG;        // FET switch connects JTAG TDI to TDO when HPU is not installed or not powered, must be powered by MB_VCC
  CM_HostPLD             HOST_PLD;          // Host CPLD
 
  CP_SN74LVTH162245     BDF_XCVR_LOW;      // Data Tranceivers to various devices
  CP_SN74LVTH162245     BDF_XCVR_HIGH;
  CP_SN74LVTH162245     BDG_XCVR;
  CP_SN74LVTH162245     BDH_XCVR_LOW;
  CP_SN74LVTH162245     BDH_XCVR_HIGH;
 
  CP_DS2401P            SerialNumber;      // motherboard's serial number
  CP_R4_7K              PullupSN;
 
  CP_R30                Term_VFIFO_WR_CLK;  // terminators for clocks and strobes
  CP_R30                Term_HFIFO_RD_CLK;
  CP_R30                Term_DPRAM_WE_N;
  CP_R30                Term_HFL_WE_N;
  CP_EXB2HV560JV        Term_DS1;
  CP_EXB2HV560JV        Term_DS2;
 
 
 
// decoupling
//   Host PLD:       cdc: 4   tdc: 0   (near XCVR, below)
//   XCVR's:         cdc: 4x5 tdc: 1x3
    enum { vcc_cdc_count  = 24,
           vcc_tdc_count  = 3  };
    CP_CDC_POS  VCC_CDC[  vcc_cdc_count  ];    // ceramic decoupling
    CP_TDC_POS  VCC_TDC[  vcc_tdc_count  ];    // tantalum decoupling
 
  virtual void Register() {
 
// bundles
    reg(  BK );
    reg(  CG );
    reg(  DC );
    reg(  DX );
    reg(  IC );
    reg(  JT );
    reg(  VME );
    reg(  MeasCtrl );
 
// ports
    reg(  MB_VCC );
    reg(  DSP_VCC );
    reg(  DSP_VB );
    reg(  DSP_VA );
    reg(  GND    );
 
    regb( BA , 21, 2 );
    regb( BDF, 31, 0 );
    regb( BDG, 15, 0 );
    regb( BDH, 31, 0 );
 
// parts and modules
    reg( HPU );
    reg( SwitchJTAG   );
 
    reg( HOST_PLD );
 
    reg( BDF_XCVR_LOW  );
    reg( BDF_XCVR_HIGH );
    reg( BDG_XCVR      );
    reg( BDH_XCVR_LOW  );
    reg( BDH_XCVR_HIGH );
 
    reg( SerialNumber  );
    reg( PullupSN      );
 
    reg( Term_VFIFO_WR_CLK );
    reg( Term_HFIFO_RD_CLK );
    reg( Term_DPRAM_WE_N   );
    reg( Term_HFL_WE_N     );
    reg( Term_DS1 );
    reg( Term_DS2 );
 
    rega( VCC_CDC, vcc_cdc_count );
    rega( VCC_TDC, vcc_tdc_count );
 
  }
 
  virtual void Connect() {
    wireall( MB_VCC, "VCC" );
    wire(    DSP_VCC );
    wire(    DSP_VB  );
    wire(    DSP_VA  );
    wireall( GND );
 
    JT.HostPLD    <<  HOST_PLD.JT;
    JT.HPU_DSP    <<  HPU.Emulator;
    JT.HPU_FPGA   <<  HPU.JTAG;
    HPU.PRESENT   <<  SwitchJTAG.OE_N;  // HPU.PRESENT is pulled low in CM_GPU
    HPU.JTAG.TDO  <<  SwitchJTAG.A;
    HPU.JTAG.TDI  <<  SwitchJTAG.B;
 
    "RAW_BD"         << HPU.EGEN(31, 0);    //Connect EGENs to XCVRs
    HPU.EGEN(15, 0)  << BDF_XCVR_LOW.B  << BDG_XCVR.B  << BDH_XCVR_LOW.B;
    HPU.EGEN(31, 16) << BDF_XCVR_HIGH.B << BDH_XCVR_HIGH.B;
 
    //XCVR Controls
    "BDF_OE_N"  << BDF_XCVR_LOW.OE_N << BDF_XCVR_HIGH.OE_N << HOST_PLD.BDF_OE_N;
    "BDG_OE_N"  << BDG_XCVR.OE_N     << HOST_PLD.BDG_OE_N;
    "BDH_OE_N"  << BDH_XCVR_LOW.OE_N << BDH_XCVR_HIGH.OE_N << HOST_PLD.BDH_OE_N;
 
    "BDF_DIR"   << BDF_XCVR_LOW.DIR  << BDF_XCVR_HIGH.DIR  << HOST_PLD.BDF_DIR;
    "BDG_DIR"   << BDG_XCVR.DIR      << HOST_PLD.BDG_DIR;
    "BDH_DIR"   << BDH_XCVR_LOW.DIR  << BDH_XCVR_HIGH.DIR  << HOST_PLD.BDH_DIR;
 
    BDH         << DX.BDH << VME.DPRAM_D; //Connect data bus
    BDH( 7, 0 ) << HOST_PLD.BDH;
 
    BDH(15, 0 ) << BDH_XCVR_LOW.A;
    BDH(31, 16) << BDH_XCVR_HIGH.A;
 
    BDF         << DX.BDF << VME.FIFO_D;
    BDF(15, 0 ) << BDF_XCVR_LOW.A;
    BDF(31, 16) << BDF_XCVR_HIGH.A;
 
    BDG         << IC.D << BDG_XCVR.A;
    BDG(7, 0)   << CG.D;
    BDG(7, 0)   << VME.FMD;
 
    BA          << HPU.EGEN(51, 32);         //Connect address bus
    BA(21, 14)  << HOST_PLD.BA;
    BA(19,  2)  << VME.FMA;
    BA(16,  2)  << VME.DPRAM_A;
    BA( 5,  2)  << DX.A << IC.A;
    BA( 3,  2)  << CG.A;
 
// Backplane
    BK.SOFTRESET_N  <<  VME.SOFTRESET_N;   // SOFTRESET_N happens to be available in Host
    BK.BUSY_N       <<  HPU.EGEN( 60 );    // BUSY_N to backplane, may need to sink > 8 mA
 
// ClockGeneration
 
    CG.HPU_CLK <<  HPU.Clocks.CLKIN;
    CG.RCLK    <<  HPU.Clocks.RCLK;
    CG.SCLK    <<  HPU.Clocks.SCLK;
    CG.DC_CLK  <<  HPU.Clocks.DC_CLK;
    CG.DX_CLK  <<  HPU.Clocks.DX_CLK;
 
// DPU_Control
    HPU.GEN( 31,  0 )  << DC.DCD_H;
    HPU.GEN( 47, 32 )  << DC.DCC_H;
 
// Data Exchange
    DX.HFIFO_REN_N                                              << HOST_PLD.HFIFO_REN_N;
    DX.HFIFO_OE_N                                               << HOST_PLD.HFIFO_OE_N;
    DX.HFIFO_RD_CLK   ^ Term_HFIFO_RD_CLK ^  "LOC_HFIFO_RD_CLK" << HOST_PLD.HFIFO_RD_CLK;
    DX.HFIFO_EF_N                                               << HOST_PLD.HFIFO_EF_N;
    DX.HFIFO_PAE_N                                              << HOST_PLD.HFIFO_PAE_N;
 
    DX.DXF_HG        << HPU.EGEN(55, 52);  // !! Check location of GENS !!
    DX.DXB_HG        << HPU.EGEN(59, 56);
 
// Interconnect
    IC.HG            << HPU.EGEN(74, 67);  // !! Check location of GENS !!
 
// power (control of power measurement)
    MeasCtrl.ASEL    << HOST_PLD.ASEL;    // GENS !! // running out of GENS --> use spare pins on HOST_PLD
    MeasCtrl.CLK     << HPU.GEN(  76 );   // GENS !! // free-running clock  --> source from XB FPGA
    MeasCtrl.SCLK    << HPU.EGEN( 66 );   // GENS !! // software-controlled clock --> source from EMIF FPGA
    MeasCtrl.DOUT    << HPU.EGEN( 65 );   // GENS !! // software-read data        --> to EMIF FPGA
 
 
    merge( "/NC", HPU.GEN(  75, 48 ) );    // GENS !!
    merge( "/NC", HPU.EGEN( 64, 61 ) );    // GENS !!
 
 
// VME Interface
    VME.HFL_A                                         << HOST_PLD.HFL_A;      // FlashPLD, flash memory
    VME.HFL_OE_N                                      << HOST_PLD.HFL_OE_N;
    VME.HFL_WE_N   ^ Term_HFL_WE_N ^  "LOC_HFL_WE_N"  << HOST_PLD.HFL_WE_N;
    VME.HFL_SPARE                                     << HOST_PLD.HFL_SPARE;
 
 
    VME.FINIT_N      << HPU.FINIT_N;
    VME.EFINIT_N     << HPU.EFINIT_N;
    VME.FDONE        << HPU.FDONE;
    VME.EFDONE       << HPU.EFDONE;
    VME.FPRGM_N      << HPU.CONF.PROGRAM0_N;
    VME.EFPRGM_N     << HPU.CONF.PROGRAM1_N;
 
    JT.CCLK          << HPU.CONF.CCLK;
    JT.DIN           << HPU.CONF.DIN;
 
    VME.DX           << HPU.DX0;
    VME.CLKX         << HPU.CLKX0;
    VME.CLKR         << HPU.CLKR0;
    VME.FSX          << HPU.FSX0;
 
    VME.HPU_RESET_N  << HPU.RESET_N;
    VME.SOFTRESET_N  << HOST_PLD.SOFTRESET_N;
 
    VME.INT          << HOST_PLD.HINT;
    VME.INTREQ       << HOST_PLD.HINTREQ;
    VME.INTPEND      << HOST_PLD.HINTPEND;
 
    VME.FIFO_WEN_N                                              << HOST_PLD.VFIFO_WEN_N;
    VME.FIFO_PAF_N                                              << HOST_PLD.VFIFO_PAF_N;
    VME.FIFO_WR_CLK   ^ Term_VFIFO_WR_CLK ^  "LOC_VFIFO_WR_CLK" << HOST_PLD.VFIFO_WR_CLK;
 
    VME.DPRAM_OE_N                                              << HOST_PLD.DP_OE_N;
    VME.DPRAM_CE_N                                              << HOST_PLD.DP_CE_N;
    VME.DPRAM_WE_N    ^ Term_DPRAM_WE_N ^    "LOC_DPRAM_WE_N"   << HOST_PLD.DP_WE_N;
    VME.DPRAM_INT_N                                             << HOST_PLD.DP_INT_N;
    VME.DPRAM_BUSY_N                                            << HOST_PLD.DP_BUSY_N;
 
// data strobes via series resistor pack
    "LOC_BPI_DS_N"  << HOST_PLD.BPI_DS_N  << Term_DS1.B( 5, 0 );   Term_DS1.A( 5, 0 )  <<  IC.BPI_STB_N;
    merge( "/NC", Term_DS1.B( 7, 6 ) );
    merge( "/NC", Term_DS1.A( 7, 6 ) );
    int i = 0;
    "LOC_TTC_DS_N"  << HOST_PLD.TTC_DS_N  << Term_DS2.B( i    );   Term_DS2.A( i++  )  <<  IC.TTC_STB_N;
    "LOC_CG_DS_N"   << HOST_PLD.CG_DS_N   << Term_DS2.B( i    );   Term_DS2.A( i++  )  <<  CG.NSTB_N;
    "LOC_DXFA_DS_N" << HOST_PLD.DXFA_DS_N << Term_DS2.B( i    );   Term_DS2.A( i++  )  <<  DX.DXF_STB_N( 0 );
    "LOC_DXFB_DS_N" << HOST_PLD.DXFB_DS_N << Term_DS2.B( i    );   Term_DS2.A( i++  )  <<  DX.DXF_STB_N( 1 );
    "LOC_DXB_DS_N"  << HOST_PLD.DXB_DS_N  << Term_DS2.B( i    );   Term_DS2.A( i++  )  <<  DX.DXB_STB_N;
    merge( "/NC", Term_DS2.B( 7, 5 ) );
    merge( "/NC", Term_DS2.A( 7, 5 ) );
 
 
// Various PLD <-> HPU Connector connections
    "AOE_N"    << HPU.AOE_N  << HOST_PLD.AOE_N;
    "ARE_N"    << HPU.ARE_N  << HOST_PLD.ARE_N;    // GPU contains series terminator
    "AWE_N"    << HPU.AWE_N  << HOST_PLD.AWE_N;    // GPU contains series terminator
    "ARDY"     << HPU.ARDY   << HOST_PLD.ARDY;
 
    "CE0_N"    << HPU.CE0_N  << HOST_PLD.CE0_N;
    "CE1_N"    << HPU.CE1_N  << HOST_PLD.CE1_N;
    "CE2_N"    << HPU.CE2_N  << HOST_PLD.CE2_N;
 
    IC.WR_N    << CG.WR_N << HOST_PLD.WR_N;
    DX.WR_N    << HOST_PLD.DX_WR_N;          // DX gets its own copy of WR_N
 
// serial number chip
    "SN_DATA"  << SerialNumber.DATA << HOST_PLD.SN_DATA  ^ PullupSN ^  MB_VCC;
    "/NC"      << SerialNumber.NC;
 
// Decoupling
    for ( int i = 0; i < vcc_cdc_count; ++ i )   MB_VCC  << VCC_CDC[ i ].POS;
    for ( int i = 0; i < vcc_tdc_count; ++ i )   MB_VCC  << VCC_TDC[ i ].POS;
 
  }
};
 
#endif
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