Coolquest, Inc. Home Products Support About Contact
cbold_logo_gif C++BOLD Example Design: TTM cbold_logo_gif

Design Home <<  File View  >> Class View Output (partial) Parts Library Examples Home

  

// THIS FILE IS IN THE PUBLIC DOMAIN.
// IT IS PROVIDED AS IS WITHOUT WARRANTY OF ANY KIND, EITHER EXPRESSED OR IMPLIED, INCLUDING, BUT
// NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE.
 
#ifndef _TTM_BackplaneH_
#define _TTM_BackplaneH_
 
#include "vme_connectors.h"
#include "rod_connectors.h"
#include "ttm_clocking.h"     // for CB_Back_CK
#include "ttm_asmlink.h"      // for several CB_'s, some through nested include's
#include "ttm_terminators.h"  // for CM_Term56x2x8
#include "sn74lvth162245.h"
#include "headers.h"
 
// All necessary decoupling capacitors are already included.
 
// CM_Backplane: ROD backplane connectors
// Some signal names had to be changed from standard VME names--search
// for "VME name" in file VME_Connectors.pt for details.
 
// CB_Pwr_Back: Interface between Power and Backplane
 
class CB_PWR_Back : public TBundle {
public:
  port VPOS3_3;     //  3.3V
  port VCC_EN;      //  VCC enable from ROD
 
  virtual void Register() {
    reg( VPOS3_3 );
    reg( VCC_EN );
  }
};
 
 
clone ( CP_VME64_P2R, CP_VME64_RP2R );  // RP2 is a female connector, P2 is male
 
class CM_Backplane : public TModule {    // Backplane Subsystem
public:
 
// ***** member bundles ***** //
  CB_Asm_Back    Asm[ 4 ];  // interface to AsmLink's
  CB_PWR_Back    Power;     // interface to Power subsystem
  CB_Back_CK     CK;        // interface to Clocking subsystem
 
// ***** member ports ***** //
  port VCC;                 // this VCC comes from the Power subsystem, not the backplane
  port GND;
  port RAW_TX;              // dummy port for assigning readable net name in CM_Root, needed because of byte swap in TX_Buffer
 
// ***** member modules and parts ***** //
//CP_VME64_P1   BAP1;  // standard VME P1
  CP_VME64_RP2R BAP2;  // VME RP2 with ROD-specific user-defined pins
//CP_ROD_J0P0   BAP0;  // ROD-specific versions of P0, P5, P6
  CP_ROD_J5P5   BAP5;
  CP_ROD_J6P6   BAP6;
 
                                  // buffers for bussed signals from backplane
  CP_SN74LVTH162245  TX_Buffer;   // >>> place near backplane
  CP_SN74LVTH162245  VarBuffer;   // >>> place near backplane
  CP_EXB2HV222JV     PullVarL;    // pull up/down for some raw (unbuffered) inputs to VarBuffer
  CP_EXB2HV222JV     PullVarH;
 
  CM_Term56x2x8      PTermTX_L;   // >>> place all PTerm's at far end of bus, opposite buffers
  CM_Term56x2x8      PTermTX_H;
  CM_Term56x2x8      PTermVarL;
  CM_Term56x2x8      PTermVarH;
 
                                      // test headers, e.g., for logic analyzer
                                      //                     >>> leave reasonable clearance around all TestHeader's, especially near pins 1, 2, 19, 20
                                      //                     >>> label all TestHeader's on silkscreen: symbolic name, pin 1, GND
  CP_HEADER10X2      TestHeaderTX_L;  // TX LSB              >>> place near TX_Buffer
  CP_HEADER10X2      TestHeaderTX_H;  // TX MSB              >>> place near TX_Buffer
  CP_HEADER10X2      TestHeaderVarL;  // Various, LSB        >>> place near VarBuffer
  CP_HEADER10X2      TestHeaderVarH;  // Various, MSB        >>> place near VarBuffer
  CP_HEADER10X2      TestHeaderRX_L;  // RX LSB (AsmLink0)   >>> place near BKP5, BKP6, or BKP2, as appropriate
  CP_HEADER10X2      TestHeaderRX_H;  // RX MSB (AsmLink0)   >>> place near BKP5, BKP6, or BKP2, as appropriate
  CP_HEADER2         TestHeaderCLK;   // clock output        >>> place near other TestHeader's
  CP_HEADER2         TestHeaderVCC;   // VCC (3.3V)          >>> place near VarBuffer, label VCC pin
 
 
  // decoupling (also important as signal return path )  >>> place near connectors as specified below
  enum {
         v3_cdc_count = +2      // >>> place near BKP5
                        +2,     // >>> place near BKP6
         v3_tdc_count =  1 };
  CP_CDC_POS  V3_CDC[ v3_cdc_count ];    // ceramic decoupling for backplane 3.3V
  CP_TDC_POS  V3_TDC[ v3_tdc_count ];    // tantalum decoupling for backplane 3.3V
 
  enum { vc_cdc_count = 8       // >>> place near TX_Buffer and MiscBuffer
                      + 4,      // >>> place near PTerm's
         vc_tdc_count = 2       // >>> place near TX_Buffer and MiscBuffer
                      + 1 };    // >>> place near PTerm's
  CP_CDC_POS  VC_CDC[ vc_cdc_count ];    // ceramic decoupling for VCC
  CP_TDC_POS  VC_TDC[ vc_tdc_count ];    // tantalum decoupling for VCC
 
 
  virtual void Register() {
// bundles
    rega( Asm, 4 );
    reg(  Power  );
    reg(  CK     );
 
// ports
    reg(  VCC );
    reg(  GND );
    regb( RAW_TX, 15, 0 );
 
// parts and modules
//  reg( BAP1 );
    reg( BAP2 );
    BAP2.SetPackage( "DIN160P_RT_INV" );      // use footprint with inverted row numbers
//    reg( BAP0 );
 
    reg( BAP5 );
    BAP5.SetPackage( "CONN_2MM_6X22_INV" );   // use footprint with inverted row numbers
 
    reg( BAP6 );
    BAP6.SetPackage( "CONN_2MM_6X25_INV" );   // use footprint with inverted row numbers
 
    reg( TX_Buffer );
    reg( VarBuffer );
    reg( PullVarL  );
    reg( PullVarH  );
    reg( PTermTX_L );
    reg( PTermTX_H );
    reg( PTermVarL );
    reg( PTermVarH );
 
    reg( TestHeaderTX_L );
    reg( TestHeaderTX_H );
    reg( TestHeaderVarL );
    reg( TestHeaderVarH );
    reg( TestHeaderRX_L );
    reg( TestHeaderRX_H );
    reg( TestHeaderCLK  );
    reg( TestHeaderVCC  );
 
    rega( V3_CDC, v3_cdc_count );
    rega( V3_TDC, v3_tdc_count );
    rega( VC_CDC, vc_cdc_count );
    rega( VC_TDC, vc_tdc_count );
  }
 
  virtual void Connect() {
//  wire( Power,    BAP1 );
//  wire( Power,    BAP2 );   // the TTM does not use the 5V on BAP2
    wire( Power,    BAP5 );
    wire( Power,    BAP6 );
//  "/NC"        << BAP1.VNEG12;       // unused voltages
//  "/NC"        << BAP1.VSTDBY5;
 
    wireall( GND );
    wireall( VCC );
    for ( int i = 0; i < v3_cdc_count; ++ i )  Power.VPOS3_3  <<  V3_CDC[ i ].POS;
    for ( int i = 0; i < v3_tdc_count; ++ i )  Power.VPOS3_3  <<  V3_TDC[ i ].POS;
    for ( int i = 0; i < vc_cdc_count; ++ i )  VCC            <<  VC_CDC[ i ].POS;
    for ( int i = 0; i < vc_tdc_count; ++ i )  VCC            <<  VC_TDC[ i ].POS;
 
    GND    << BAP2.TMP_N;    // transition module presence indicator
 
//  wire( CK, BAP0 );    // clocks to/from backplane
    wire( CK, BAP5 );
//  wire( CK, BAP6 );
 
 
// BG location summary:
//  P2 (40 total):  BG_B0[15:0]          // RX
//                  BG_A0[15:0]          // RX
//                  BG_B1[15:8]
 
//  P5 (72 total):  BG_B1[ 7:0]
//                  BG_A1[15:0]
//                  BG_B2[15:0]          // RX
//                  BG_A2[15:0]          // RX
//                  BG_B3[15:0]          // RX
 
//  P6 (80 total):  BG_A3[15:0]          // RX
//                  BG_B4[15:0]
//                  BG_A4[15:0]
//                  BG_B5[15:0]          // RX
//                  BG_A5[15:0]          // RX
 
// *** Point-to-Point AsmLink Connections *** //
 
// RX (parallel data to RX)
    "B0_RX"  <<  Asm[ 0 ].RxB.PtToPt.RX  <<  BAP2.BG_B0;
    "A0_RX"  <<  Asm[ 0 ].RxA.PtToPt.RX  <<  BAP2.BG_A0;
 
    "B1_RX"  <<  Asm[ 1 ].RxB.PtToPt.RX  <<  BAP5.BG_B2;
    "A1_RX"  <<  Asm[ 1 ].RxA.PtToPt.RX  <<  BAP5.BG_A2;
 
    "B2_RX"  <<  Asm[ 2 ].RxB.PtToPt.RX  <<  BAP5.BG_B3;
    "A2_RX"  <<  Asm[ 2 ].RxA.PtToPt.RX  <<  BAP6.BG_A3;
 
    "B3_RX"  <<  Asm[ 3 ].RxB.PtToPt.RX  <<  BAP6.BG_B5;
    "A3_RX"  <<  Asm[ 3 ].RxA.PtToPt.RX  <<  BAP6.BG_A5;
 
// All other point-to-point connections
// On the ROD, these connect to shared lines on BPI_FPGA1 and BPI_FPGA4
 
    int i = 0;
    "A0_RXFLAG"   <<  Asm[ 0 ].RxA.PtToPt.RXFLAG   <<  BAP5.BG_A1( i );  i++;      // BG_A1 is shared with BPI_FPGA0
    "A0_RXDATA"   <<  Asm[ 0 ].RxA.PtToPt.RXDATA   <<  BAP5.BG_A1( i );  i++;
    "A0_RXERROR"  <<  Asm[ 0 ].RxA.PtToPt.RXERROR  <<  BAP5.BG_A1( i );  i++;
    "A0_RXREADY"  <<  Asm[ 0 ].RxA.PtToPt.RXREADY  <<  BAP5.BG_A1( i );  i++;
 
    "B0_RXFLAG"   <<  Asm[ 0 ].RxB.PtToPt.RXFLAG   <<  BAP5.BG_A1( i );  i++;
    "B0_RXDATA"   <<  Asm[ 0 ].RxB.PtToPt.RXDATA   <<  BAP5.BG_A1( i );  i++;
    "B0_RXERROR"  <<  Asm[ 0 ].RxB.PtToPt.RXERROR  <<  BAP5.BG_A1( i );  i++;
    "B0_RXREADY"  <<  Asm[ 0 ].RxB.PtToPt.RXREADY  <<  BAP5.BG_A1( i );  i++;
 
    i = 0;
    "A1_RXFLAG"   <<  Asm[ 1 ].RxA.PtToPt.RXFLAG   <<  BAP5.BG_B1( i );  i++;      // BG_B1 is shared with BPI_FPGA2
    "A1_RXDATA"   <<  Asm[ 1 ].RxA.PtToPt.RXDATA   <<  BAP5.BG_B1( i );  i++;
    "A1_RXERROR"  <<  Asm[ 1 ].RxA.PtToPt.RXERROR  <<  BAP5.BG_B1( i );  i++;
    "A1_RXREADY"  <<  Asm[ 1 ].RxA.PtToPt.RXREADY  <<  BAP5.BG_B1( i );  i++;
 
    "B1_RXFLAG"   <<  Asm[ 1 ].RxB.PtToPt.RXFLAG   <<  BAP5.BG_B1( i );  i++;
    "B1_RXDATA"   <<  Asm[ 1 ].RxB.PtToPt.RXDATA   <<  BAP5.BG_B1( i );  i++;
    "B1_RXERROR"  <<  Asm[ 1 ].RxB.PtToPt.RXERROR  <<  BAP5.BG_B1( i );  i++;
    "B1_RXREADY"  <<  Asm[ 1 ].RxB.PtToPt.RXREADY  <<  BAP5.BG_B1( i );  i++;
 
    i = 0;
    "A2_RXFLAG"   <<  Asm[ 2 ].RxA.PtToPt.RXFLAG   <<  BAP6.BG_A4( i );  i++;      // BG_A4 is shared with BPI_FPGA3
    "A2_RXDATA"   <<  Asm[ 2 ].RxA.PtToPt.RXDATA   <<  BAP6.BG_A4( i );  i++;
    "A2_RXERROR"  <<  Asm[ 2 ].RxA.PtToPt.RXERROR  <<  BAP6.BG_A4( i );  i++;
    "A2_RXREADY"  <<  Asm[ 2 ].RxA.PtToPt.RXREADY  <<  BAP6.BG_A4( i );  i++;
 
    "B2_RXFLAG"   <<  Asm[ 2 ].RxB.PtToPt.RXFLAG   <<  BAP6.BG_A4( i );  i++;
    "B2_RXDATA"   <<  Asm[ 2 ].RxB.PtToPt.RXDATA   <<  BAP6.BG_A4( i );  i++;
    "B2_RXERROR"  <<  Asm[ 2 ].RxB.PtToPt.RXERROR  <<  BAP6.BG_A4( i );  i++;
    "B2_RXREADY"  <<  Asm[ 2 ].RxB.PtToPt.RXREADY  <<  BAP6.BG_A4( i );  i++;
 
    i = 0;
    "A3_RXFLAG"   <<  Asm[ 3 ].RxA.PtToPt.RXFLAG   <<  BAP6.BG_B4( i );  i++;      // BG_B4 is shared with BPI_FPGA5
    "A3_RXDATA"   <<  Asm[ 3 ].RxA.PtToPt.RXDATA   <<  BAP6.BG_B4( i );  i++;
    "A3_RXERROR"  <<  Asm[ 3 ].RxA.PtToPt.RXERROR  <<  BAP6.BG_B4( i );  i++;
    "A3_RXREADY"  <<  Asm[ 3 ].RxA.PtToPt.RXREADY  <<  BAP6.BG_B4( i );  i++;
 
    "B3_RXFLAG"   <<  Asm[ 3 ].RxB.PtToPt.RXFLAG   <<  BAP6.BG_B4( i );  i++;
    "B3_RXDATA"   <<  Asm[ 3 ].RxB.PtToPt.RXDATA   <<  BAP6.BG_B4( i );  i++;
    "B3_RXERROR"  <<  Asm[ 3 ].RxB.PtToPt.RXERROR  <<  BAP6.BG_B4( i );  i++;
    "B3_RXREADY"  <<  Asm[ 3 ].RxB.PtToPt.RXREADY  <<  BAP6.BG_B4( i );  i++;
 
    i = 8;  // TG(7,0) are reserved for connection to TIM's TTC() outputs via a custom J5/J6 backplane
    "A0_SD"       <<  Asm[ 0 ].SD_A                <<  BAP6.TG( i );  i++;     // signal detects from optical transceivers
    "B0_SD"       <<  Asm[ 0 ].SD_B                <<  BAP6.TG( i );  i++;
    "A1_SD"       <<  Asm[ 1 ].SD_A                <<  BAP6.TG( i );  i++;
    "B1_SD"       <<  Asm[ 1 ].SD_B                <<  BAP6.TG( i );  i++;
    "A2_SD"       <<  Asm[ 2 ].SD_A                <<  BAP6.TG( i );  i++;
    "B2_SD"       <<  Asm[ 2 ].SD_B                <<  BAP6.TG( i );  i++;
    "A3_SD"       <<  Asm[ 3 ].SD_A                <<  BAP6.TG( i );  i++;
    "B3_SD"       <<  Asm[ 3 ].SD_B                <<  BAP6.TG( i );  i++;
 
 
 
 
// *** Bussed AsmLink Connections *** //
 
    for ( int i = 0; i < 4; ++ i ) {
      ""    << Asm[ i ].RxA.Bussed;
      ""    << Asm[ i ].RxB.Bussed;
      ""    << Asm[ i ].Tx.Bussed;
      "/NC" << Asm[ i ].Tx.PtToPt.TXLOCKED;
    }
 
 
// pull backplane connections to default level
//                                        output                  input
    Asm[ 0 ].Tx.Bussed.TX(  7, 0 )  <<  TX_Buffer.B( 15, 8 );  // (see inputs below)
    Asm[ 0 ].Tx.Bussed.TX( 15, 8 )  <<  TX_Buffer.B(  7, 0 );
// TX_Buffer inputs
// do this last to avoid "two of a module's ports cannot share a common internal connection" exception (bug in cbold?)
    RAW_TX(  7, 0 )  <<  TX_Buffer.A( 15, 8 );  // (see inputs below)
    RAW_TX( 15, 8 )  <<  TX_Buffer.A(  7, 0 );
 
    i = 8;
    Asm[ 0 ].Tx.Bussed.TXDIV0       <<  VarBuffer.B( i );      VarBuffer.A( i )     << "RAW_TXDIV0";      PullVarL.B(  i - 8 ) << VCC; i++;
    Asm[ 0 ].Tx.Bussed.TXDIV1       <<  VarBuffer.B( i );      VarBuffer.A( i )     << "RAW_TXDIV1";      PullVarL.B(  i - 8 ) << GND; i++;
    Asm[ 0 ].Tx.Bussed.TXFLGENB     <<  VarBuffer.B( i );      VarBuffer.A( i )     << "RAW_TXFLGENB";    PullVarL.B(  i - 8 ) << GND; i++;
    Asm[ 0 ].Tx.Bussed.TXESMPXENB   <<  VarBuffer.B( i );      VarBuffer.A( i )     << "RAW_TXESMPXENB";  PullVarL.B(  i - 8 ) << GND; i++;
    Asm[ 0 ].Tx.Bussed.TXFLAG       <<  VarBuffer.B( i );      VarBuffer.A( i )     << "RAW_TXFLAG";      PullVarL.B(  i - 8 ) << GND; i++;
    Asm[ 0 ].Tx.Bussed.TXDATA       <<  VarBuffer.B( i );      VarBuffer.A( i )     << "RAW_TXDATA";      PullVarL.B(  i - 8 ) << VCC; i++;
    Asm[ 0 ].Tx.Bussed.TXCNTL       <<  VarBuffer.B( i );      VarBuffer.A( i )     << "RAW_TXCNTL";      PullVarL.B(  i - 8 ) << GND; i++;
    "UNUSED15"                      <<  VarBuffer.B( i );      VarBuffer.A( i )     << "RAW_UNUSED15";    PullVarL.B(  i - 8 ) << VCC; i++;    // skip one pin --> RX and TX in separate byte
 
    i = 0;
    Asm[ 0 ].RxA.Bussed.RXDIV0      <<  VarBuffer.B( i );      VarBuffer.A( i )     << "RAW_RXDIV0";      PullVarH.B(  i     ) << VCC; i++;
    Asm[ 0 ].RxA.Bussed.RXDIV1      <<  VarBuffer.B( i );      VarBuffer.A( i )     << "RAW_RXDIV1";      PullVarH.B(  i     ) << GND; i++;
    Asm[ 0 ].RxA.Bussed.RXFLGENB    <<  VarBuffer.B( i );      VarBuffer.A( i )     << "RAW_RXFLGENB";    PullVarH.B(  i     ) << GND; i++;
    Asm[ 0 ].RxA.Bussed.RXESMPXENB  <<  VarBuffer.B( i );      VarBuffer.A( i )     << "RAW_RXESMPXENB";  PullVarH.B(  i     ) << GND; i++;
 
    "BUF_VCC_EN"                    <<  VarBuffer.B( i );      VarBuffer.A( i )     << "VCC_EN";          PullVarH.B(  i     ) << GND; i++;  // do not use buffered version of VCC_EN, because buffer has no power until VCC is enabled
    "OSC_EN"  <<  CK.OSC_EN         <<  VarBuffer.B( i );      VarBuffer.A( i )     << "RAW_OSC_EN";      PullVarH.B(  i     ) << VCC; i++;
    "UNUSED"                        <<  VarBuffer.B( 7, i );   VarBuffer.A( 7, i ) << "RAW_UNUSED";
 
    "VCC_EN"  <<  Power.VCC_EN;   // TTM_Power contains a jumper to override the pull-down
                                                                                              merge( VCC, PullVarH.B( 7, i ) );
 
    VarBuffer.A( 15, 8 )  <<  PullVarL.A;   // resistor packs for pullup/pulldown
    VarBuffer.A(  7, 0 )  <<  PullVarH.A;
 
 
 
    RAW_TX(  7, 0 )       <<  BAP5.BG_A1( 15, 8 );      // connections from BPI_FPGA1
    RAW_TX( 15, 8 )       <<  BAP6.BG_A4( 15, 8 );      // connections from BPI_FPGA4
    VarBuffer.A( 15, 8 )  <<  BAP2.BG_B1( 15, 8 );      // connections from BPI_FPGA1
    VarBuffer.A(  7, 0 )  <<  BAP6.BG_B4( 15, 8 );      // connections from BPI_FPGA4
 
 
                                // buffer's B port can sink 64 mA, A port has 22 ohm series resistors and can only sink 12 mA
    VCC  <<  TX_Buffer.DIR;     // DIR = 1 --> A data to B bus
    VCC  <<  VarBuffer.DIR;
    GND  <<  TX_Buffer.OE_N;
    GND  <<  VarBuffer.OE_N;
 
 
 
    TX_Buffer.B( 15, 8 )  << PTermTX_L.A;         // parallel termination for bussed signals
    TX_Buffer.B(  7, 0 )  << PTermTX_H.A;
    VarBuffer.B( 15, 8 )  << PTermVarL.A;
    VarBuffer.B(  7, 0 )  << PTermVarH.A;
 
    merge( VCC, PTermTX_L.B );
    merge( VCC, PTermTX_H.B );
    merge( VCC, PTermVarL.B );
    merge( VCC, PTermVarH.B );
 
 
// *** TestHeader's *** //
 
    int odd = 1, even = 2;
    for ( int i = 0; i < 8; ++ i ) {
      GND                              << TestHeaderTX_L.P( even );    // all even pins are grounded
      GND                              << TestHeaderTX_H.P( even );
      GND                              << TestHeaderVarL.P( even );
      GND                              << TestHeaderVarH.P( even );
      GND                              << TestHeaderRX_L.P( even );
      GND                              << TestHeaderRX_H.P( even );
      RAW_TX(                 i     )  << TestHeaderTX_L.P(  odd );
      RAW_TX(                 i + 8 )  << TestHeaderTX_H.P(  odd );
      VarBuffer.A(            i + 8 )  << TestHeaderVarL.P(  odd );
      VarBuffer.A(            i     )  << TestHeaderVarH.P(  odd );
      Asm[ 0 ].RxA.PtToPt.RX( i     )  << TestHeaderRX_L.P(  odd );    // additional connections below
      Asm[ 0 ].RxA.PtToPt.RX( i + 8 )  << TestHeaderRX_H.P(  odd );    // additional connections below
      even += 2;
      odd  += 2;
    }
    VCC                                << TestHeaderVCC.P( 1 );
    CK.TEST_CLK                        << TestHeaderCLK.P( 1 );
    GND                                << TestHeaderVCC.P( 2 );
    GND                                << TestHeaderCLK.P( 2 );
 
 
    for ( int i = 0; i < 2; ++ i ) {                                   // NC's, additional grounds
      GND                              << TestHeaderTX_L.P( even );    // all even pins are grounded
      GND                              << TestHeaderTX_H.P( even );
      GND                              << TestHeaderVarL.P( even );
      GND                              << TestHeaderVarH.P( even );
      GND                              << TestHeaderRX_L.P( even );
      GND                              << TestHeaderRX_H.P( even );
      "/NC"                            << TestHeaderTX_L.P(  odd );
      "/NC"                            << TestHeaderTX_H.P(  odd );
      "/NC"                            << TestHeaderVarL.P(  odd );
      "/NC"                            << TestHeaderVarH.P(  odd );
      even += 2;
      odd  += 2;
    }
 
    "A0_RXFLAG"                        << TestHeaderRX_L.P( 17 );     // additional RX connections
    "A0_RXDATA"                        << TestHeaderRX_L.P( 19 );
    "A0_RXERROR"                       << TestHeaderRX_H.P( 17 );
    "A0_RXREADY"                       << TestHeaderRX_H.P( 19 );
 
 
//  "/NC"  << BAP0.NC;  // spares
    "/NC"  << BAP2.NC;
 
 
// the remainder of this function wires up no-connects
 
    wireall( "/NC", "VPOS5" );
    "/NC"  <<  BAP2.VPC;
 
    merge( "/NC", BAP2.D );     // no VME connections on TTM
    merge( "/NC", BAP2.A );
    "/NC"  <<  BAP2.RETRY_N;
 
    "/NC"  <<  BAP2.TMS;       // no JTAG on TTM
    "/NC"  <<  BAP2.TDI;
    "/NC"  <<  BAP2.TDO;
    "/NC"  <<  BAP2.TCK;
 
    "/NC"  <<  BAP2.CCLK;      // no FPGA's on TTM
    "/NC"  <<  BAP2.DIN;
    "/NC"  <<  BAP2.PROGRAM0_N;
    "/NC"  <<  BAP2.PROGRAM1_N;
 
    "/NC"  <<  BAP2.RESET_N;   // nothing to reset on TTM
 
 
    "/NC"  <<  BAP5.RCLKIP;    // these are inputs to the ROD
    "/NC"  <<  BAP5.RCLKIN;
 
    "/NC"  <<  BAP5.SCLKOP;    // these are outputs from the ROD
    "/NC"  <<  BAP5.SCLKON;
    "/NC"  <<  BAP5.TCLKOP;
    "/NC"  <<  BAP5.TCLKON;
    "/NC"  <<  BAP5.BUSY_N;
 
 
    "/NC"  <<  BAP6.TCLKIP;    // these are inputs to the ROD
    "/NC"  <<  BAP6.TCLKIN;
 
    merge( "/NC", BAP6.TG( 7, 0 ) );  // reserved for TTC() connections from TIM
 
  }
};
 
#endif

 

Design Home <<  File View  >> Class View Output (partial) Parts Library Examples Home

Legal Copyright © 2007 by Coolquest, Inc. Contact