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// THIS FILE IS IN THE PUBLIC DOMAIN.
// IT IS PROVIDED AS IS WITHOUT WARRANTY OF ANY KIND, EITHER EXPRESSED OR IMPLIED, INCLUDING, BUT
// NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE.
 
#ifndef _PowerH_
#define _PowerH_
 
#include "shunt_ovp.h"
#include "multiswitch.h"
#include "measure.h"
#include "switches.h"
#include "headers.h"
#include "irod_supervisor.h"
#include "lv_comparator.h"
#include "dcdc.h"
#include "monopins.h"
 
// >>> VB was formerly the separate supplies DSP_VB and MB_VB
 
// CM_Power:
// This design can tolerate an absolute max of 6.0 V on BK.VPOS5 and BK.VPOS3_3.
 
// The user must supply all desired decoupling capacitors on output voltages.
// The backplane subsystem supplies decoupling capacitors on:
//   BK.VPOS3_3
//   BK.VPOS5
// Unless it is used elsewhere in the system, the user should not add any decoupling to:
//   BK.VPOS12
 
// CB_VME_PWR:  the flash CPLD in VME subystem controls power
class CB_VME_PWR : public TBundle {
public:
                     // power enables
  port PENA;         // DSP VA
  port PENC;         // DSP VCC
  port PENB;         // VB
  port PENB_SURGE;   // VB initial surge
 
                     // when HARDRESET_N is high, motherboard VCC and VCC5 are above threshold
  port HARDRESET_N;  // hard reset to VME PLD's, active on power-up and/or watchdog expiration and/or SYSRESET_N
  port MBPWR_MR_N;   // reset to motherboard power supervisor from FlashPLD, e.g., activated after digital watchdog has expired
 
  port DSP_VAOK;     // DSP_VA  is above threshold
  port DSP_VCOK;     // DSP_VCC is above threshold
  port VBOK;         // VB      is above threshold
 
  port ONE_O;        // one-shot used to bootstrap DSP_VCC and DSP_VA
  port ONE_MR_N;     // trigger for one-shot
 
  virtual void Register() {
    reg( PENA );
    reg( PENC );
    reg( PENB );
    reg( PENB_SURGE   );
 
    reg( HARDRESET_N  );
    reg( MBPWR_MR_N   );
 
    reg( DSP_VAOK     );
    reg( DSP_VCOK     );
    reg( VBOK         );
 
    reg( ONE_O        );
    reg( ONE_MR_N     );
  }
};
 
 
class CM_Power : public TModule {    // Power Subsystem
public:
// ***** member bundles ***** //
                                 // interfaces to other subsystems
  CB_VME_PWR        VME;         // VME:              signals for controlling (enabling and disabling) power
  CB_MeasureControl MeasCtrl;    // Host:             signals for measurement of voltages and current
  CB_PWR_Back       BK;          // Backplane:        voltages from the backplane (inputs to this subsystem)
  CB_PWR_CG         CG;          // ClockGeneration:  some clocks are disabled until power is up
 
// ***** member ports ***** //
 
// motherboard supply voltages (outputs from this subsystem)
  port MB_VCC5;    // VCC5: 5V
  port MB_VCC;     // VCC:  3.3 V
  port VPC;        // precharge voltage, used only by VME transceivers
 
// DSP module supply voltages (outputs from this subsystem)
  port DSP_VCC;    // VCC:  3.3 V
  port DSP_VA;     // VA, typical use:  1.8 V for DSP VCORE
 
// share supply voltage (output from this subsystem)
  port VB;         // VB, typical use:  2.5V for FPGA VCCINT
  port GND;
 
 
// ***** member modules and parts ***** //
 
  CP_HEADER10X2CS  AuxPower;    // auxiliary power connector:  9A max per voltage
 
  CP_R1K           Pulldown[ 5 ];  // pulldowns for switch enables
  CP_R30           SeriesVPC;      // series resistor for VPC, serves as a fuse
  CP_R1K           Raux_VPC;       // resistor between VPC and VPOS5 --> VPC is powered when using auxiliary power connector
                                   // 1Kohm * 6 * 20 uA = .12V (assumes VME interface is inactive -> little current through pullups to VPC)
 
// Front panel switch and overriding header
  CP_HEADER2       LatchSwitch;
  CP_HEADER2       LatchOverride;
 
// Supervisors and Comparator
  CM_Supervisor5_3  Super_VCOK;     // monitors DSP VCC
  CM_Supervisor5_3  Super_MBPWROK;  // monitors motherboard VCC and VCC5
  CM_Supervisor5_3  Super_VINOK;    // monitors BK.VPOS3_3 and BK.VPOS5
  CM_Supervisor5_3  Super_ONE;      // used as ~ 1s one-shot
  CM_LV_Comparator  Comp_VAOK;      // monitors DSP VA
  CM_LV_Comparator  Comp_VBOK;      // monitors VB
 
// DC-to-DC Converters
  CM_DCDC_7711     DCDC_DSP_VA;
  CM_DCDC_7711     DCDC_VB;
 
// Overvoltage Protection
  CM_ShuntOVP_8A   OVP_MB_VCC5;     // motherboard
  CM_ShuntOVP_8A   OVP_MB_VCC;
 
  CM_ShuntOVP_8A   OVP_DSP_VCC;     // dsp modules
  CM_ShuntOVP_24A  OVP_DSP_VA;
 
  CM_ShuntOVP_24A  OVP_VB;          // both
 
  CM_ShuntOVP_16A  OVP_SW5_VB;      // inputs to DC-to-DC converters
  CM_ShuntOVP_16A  OVP_SW5_DVA;
 
// Voltage Measurement
 
  CM_Measure  Measure;
 
// Power switches                // list these last in case switch counts change
  CM_MultiSwitch4   SW_DSP_VCC;   // each voltage has one spare switch >>> do not install one switch per voltage
  CM_MultiSwitch4   SW_MB_VCC;
  CM_MultiSwitch2   SW_MB_VCC5;
  CM_MultiSwitch5   SW_DSP_VA;    // switches on inputs to DC-DC converters
  CM_MultiSwitch4   SW_VB;
  CM_MultiSwitch2   SW_VB_SURGE;  // enabled during initial current surge only  >>> no spare switch, install both switches
 
  enum { mono_count = 4 };             // large monopins for connecting power planes
  CP_MONOPIN60     Mono[ mono_count ];
 
  virtual void Register() {
// bundles
    reg( VME  );
    reg( MeasCtrl );
    reg( BK   );
    reg( CG   );
 
// ports
    reg( MB_VCC5 );
    reg( MB_VCC );
    reg( VPC   );
 
    reg( DSP_VCC );
    reg( DSP_VA );
 
    reg( VB );
    reg( GND );
 
// parts and modules
    reg(  AuxPower    );
 
    rega( Pulldown, 5 );
    reg(  SeriesVPC   );
    reg(  Raux_VPC    );
 
    reg( LatchSwitch   );
    reg( LatchOverride );
 
    reg( Super_VCOK    );
    reg( Super_MBPWROK );
    reg( Super_VINOK   );
    reg( Super_ONE     );
    reg( Comp_VAOK     );
    reg( Comp_VBOK     );
 
    reg( DCDC_DSP_VA );
    reg( DCDC_VB );
 
    reg( OVP_MB_VCC5 );
    reg( OVP_MB_VCC );
    reg( OVP_DSP_VCC );
    reg( OVP_DSP_VA );
    reg( OVP_VB );
 
    reg( OVP_SW5_VB );
    reg( OVP_SW5_DVA );
 
    reg( Measure     );
    reg( SW_DSP_VCC  );
    reg( SW_MB_VCC   );
    reg( SW_MB_VCC5  );
    reg( SW_DSP_VA   );
    reg( SW_VB       );
    reg( SW_VB_SURGE );
    rega( Mono, mono_count );
  }
 
  virtual void Connect() {
    wireall( GND );
 
    int mp = 0;                  // large monopins for connecting power planes
    BK.VPOS3_3 ^ Mono[ mp++ ];
    BK.VPOS3_3 ^ Mono[ mp++ ];
    VB         ^ Mono[ mp++ ];
    VB         ^ Mono[ mp++ ];
 
                                              // the installed connector may be either a 10x1 x 3-amp or 10x2 x 1-amp connector
// aux power connector:                       //  cols    1 row x 3A/pin     2 row x 1A/pin
    merge( BK.VPOS5,   AuxPower.P(  6,  1 ) );  //     3                9A                 6A
    merge( GND,        AuxPower.P( 16,  7 ) );  //     5               15A                10A
    merge( BK.VPOS3_3, AuxPower.P( 20, 17 ) );  //     2                6A                 4A
 
// VPC to VME transceivers via series resistor (fuse), Raux_VPC is only relevant when powering from AuxPower connector
    VPC ^ SeriesVPC ^ BK.VPC ^ Raux_VPC ^ BK.VPOS5;
 
 
// switch connections
    "MB_ENABLE"     ^ Pulldown[ 0 ] ^  GND;   // switch enables are inactive unless driven high
    VME.PENA        ^ Pulldown[ 1 ] ^  GND;
    VME.PENC        ^ Pulldown[ 2 ] ^  GND;
    VME.PENB        ^ Pulldown[ 3 ] ^  GND;
    VME.PENB_SURGE  ^ Pulldown[ 4 ] ^  GND;
 
    BK.VPOS3_3   << SW_DSP_VCC.IN;
    DSP_VCC      << SW_DSP_VCC.OUT;
    VME.PENC     << SW_DSP_VCC.EN;   // DSP_VCC power enable
 
    BK.VPOS3_3   << SW_MB_VCC.IN;
    MB_VCC       << SW_MB_VCC.OUT;
    "MB_ENABLE"  << SW_MB_VCC.EN;    // front panel latch enables MB_VCC and MB_VCC5
 
    BK.VPOS5     << SW_MB_VCC5.IN;
    MB_VCC5      << SW_MB_VCC5.OUT;
    "MB_ENABLE"  << SW_MB_VCC5.EN;   // front panel latch enables MB_VCC and MB_VCC5
 
    BK.VPOS5     << SW_DSP_VA.IN;
    "SW5_DVA"    << SW_DSP_VA.OUT;
    VME.PENA     << SW_DSP_VA.EN;    // DSP_VA power enable
 
    BK.VPOS5     << SW_VB.IN;
    "SW5_VB"     << SW_VB.OUT;
    VME.PENB     << SW_VB.EN;             // VB power enable
 
    BK.VPOS5        << SW_VB_SURGE.IN;    // additional VB switches, enabled only during initial current surge
    "SW5_VB"        << SW_VB_SURGE.OUT;
    VME.PENB_SURGE  << SW_VB_SURGE.EN;    // VB_SURGE power enable
 
// Supervisor and Comparator connections
    DSP_VCC          << Super_VCOK.VCC;
    MB_VCC5          << Super_VCOK.VCC5;
    VME.DSP_VCOK     << Super_VCOK.RESET_N;
    CG.DSP_VCOK      << Super_VCOK.RESET_N;
    "/NC"            << Super_VCOK.MR_N << Super_VCOK.WDI << Super_VCOK.RESET;
 
    MB_VCC           << Super_MBPWROK.VCC;
    MB_VCC5          << Super_MBPWROK.VCC5;
    VME.HARDRESET_N  << Super_MBPWROK.RESET_N;  // reset output to VME PLD's
    VME.MBPWR_MR_N   << Super_MBPWROK.MR_N;     // reset input from VMEbus
    "/NC"            << Super_MBPWROK.WDI << Super_MBPWROK.RESET;
 
    BK.VPOS3_3       << Super_VINOK.VCC;
    BK.VPOS5         << Super_VINOK.VCC5;
    "/NC"            << Super_VINOK.MR_N << Super_VINOK.WDI << Super_VINOK.RESET;
 
// front-panel latch switch and overriding header
// install jumper to permanently enable motherboard power regardless of front panel switch
    "VIN_OK"         << LatchSwitch.P( 1 )  <<  LatchOverride.P( 1 )  << Super_VINOK.RESET_N;
    "MB_ENABLE"      << LatchSwitch.P( 2 )  <<  LatchOverride.P( 2 );
 
// The CPLD code must re-assert MR_N once the watchdog expires.
// Otherwise, the supervisor will repeatedly toggle RESET_N.
// PED      ____------------------------------____   // VME-controlled Power Enable DSP
// MR_N     ____---------------------_____________
// RESET_N  _____--------------------_____________
// temp     _________________________---------____
 
// temp is cleared when PED is low, is set by the falling edge of RESET_N
// MR_N =   PED * !temp
 
    MB_VCC         << Super_ONE.VCC;
    MB_VCC5        << Super_ONE.VCC5;
    VME.ONE_MR_N   << Super_ONE.MR_N;        // a pulse on ONE_MR_N resets the watchdog
    VME.ONE_O      << Super_ONE.RESET_N;     // ONE_O pulses high for ~ 1.5s after ONE_MR_N is pulsed
    GND            << Super_ONE.WDI;         // do not service watchdog
    "/NC"          << Super_ONE.RESET;
 
    MB_VCC         << Comp_VAOK.VCC;
    DSP_VA         << Comp_VAOK.IN;
    VME.DSP_VAOK   << Comp_VAOK.OUT;   // high when VA > threshold determined by RAdjust
    Comp_VAOK.RAdjust.SetTypeName( "CP_R6_19KP1" );   // 1.62V   >>> change this resistor if DSP_VA is no longer 1.8V
 
    MB_VCC         << Comp_VBOK.VCC;
    VB             << Comp_VBOK.IN;
    VME.VBOK       << Comp_VBOK.OUT;   // high when VB > threshold determined by RAdjust
    Comp_VBOK.RAdjust.SetTypeName( "CP_R3_83KP1" );   // 2.25V   >>> change this resistor if VB is no longer 2.5V
 
// DC-to-DC converter connections
    "SW5_DVA"      << DCDC_DSP_VA.VIN;    // power in:  switched BK.VPOS5
    "SW5_VB"       << DCDC_VB.VIN;
 
    DSP_VA         << DCDC_DSP_VA.VOUT;   // power out
    VB             << DCDC_VB.VOUT;
 
 
// Overvoltage Protection
    MB_VCC5        << OVP_MB_VCC5.Vp;
    MB_VCC         << OVP_MB_VCC.Vp;
    VB             << OVP_VB.Vp;
 
    DSP_VCC        << OVP_DSP_VCC.Vp;
    DSP_VA         << OVP_DSP_VA.Vp;
 
    "SW5_VB"       << OVP_SW5_VB.Vp;
    "SW5_DVA"      << OVP_SW5_DVA.Vp;
 
 
    // OVP thresholds: change generic resistors to appropriate values
    OVP_MB_VCC5.Radjust.SetTypeName( "CP_R3_09KP1" );   // 5.3V
     OVP_MB_VCC.Radjust.SetTypeName( "CP_R5_23KP1" );   // 3.6V
 
    OVP_DSP_VCC.Radjust.SetTypeName( "CP_R5_23KP1" );   // 3.6V
     OVP_DSP_VA.Radjust.SetTypeName( "CP_R18_2KP1" );   // 1.9V
 
         OVP_VB.Radjust.SetTypeName( "CP_R8_45KP1" );   // 2.7V
 
    OVP_SW5_DVA.Radjust.SetTypeName( "CP_R3_09KP1" );   // 5.3V
     OVP_SW5_VB.Radjust.SetTypeName( "CP_R3_09KP1" );   // 5.3V
 
    // measurement system
    BK.VPOS12 << Measure.VCC12;    // CM_Measure is entirely powered from VCC12
    MeasCtrl  << Measure.MeasCtrl;
 
    "/NC"                                    << Measure.AIN( 13 );  // CM_Measure includes series resistors on AIN
    "/NC"                                    << Measure.AIN( 12 );
    "/NC"                                    << Measure.AIN( 11 );
                      BK.VPOS5               << Measure.AIN( 10 );
                      BK.VPOS3_3             << Measure.AIN(  9 );
                      MB_VCC5                << Measure.AIN(  8 );
                      MB_VCC                 << Measure.AIN(  7 );
                      DSP_VCC                << Measure.AIN(  6 );
 
    "SW5_DVA"                                << Measure.AIN(  5 );   // inputs to DC-DC converters
    "SW5_VB"                                 << Measure.AIN(  4 );
 
    "SENSE_DSP_VA" << DCDC_DSP_VA.SENSE_VOUT << Measure.AIN(  3 );
                      DSP_VA                 << Measure.AIN(  2 );
 
    "SENSE_VB"     << DCDC_VB.SENSE_VOUT     << Measure.AIN(  1 );
                      VB                     << Measure.AIN(  0 );
  }
};
 
#endif

 

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