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C++BOLD Example Design: IROD

// THIS FILE IS IN THE PUBLIC DOMAIN.
// IT IS PROVIDED AS IS WITHOUT WARRANTY OF ANY KIND, EITHER EXPRESSED OR IMPLIED, INCLUDING, BUT
// NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE.
 
#ifndef _T_VMESubSystemH_
#define _T_VMESubSystemH_
 
#include "vme_buffers.h"
#include "vmec_pld.h"
#include "vmed_pld.h"
#include "cy7c057v.h"
#include "rod_clones.h"
#include "backplane.h"
#include "std_fifo.h"
#include "flash_pld.h"
#include "am29lv033c.h"
#include "front_panel.h"  // for CB_Front_VME
 
class CB_Host_VME : public TBundle {
public:
 
  //Define ports
  //Flash Memory Controls
  port HFL_A;
  port HFL_OE_N;
  port HFL_WE_N;
  port HFL_SPARE;
  port FMD;
  port FMA;
 
  // all HPU FPGA Configuration Signals except CCLK and DIN are attached to the FlashPLD
 
  port FINIT_N;     // for HPU's XB FPGA
  port FDONE;
  port FPRGM_N;
 
  port EFINIT_N;    // for HPU's EMIF FPGA
  port EFDONE;
  port EFPRGM_N;
 
 
  //DSP Serial Port
  port DX;
  port CLKX;
  port CLKR;
  port FSX;
 
  //Resets
  port HPU_RESET_N;  // reset HPU's DSP
  port SOFTRESET_N;  // reset Host PLD
 
  //Host VME Interrupt
  port INT;
  port INTREQ;
  port INTPEND;
 
  //Host FIFO Signals
  port FIFO_WEN_N;
  port FIFO_PAF_N;
  port FIFO_WR_CLK;
  port FIFO_D;
 
  //Dual-Port RAM Signals
  port DPRAM_OE_N;
  port DPRAM_CE_N;
  port DPRAM_WE_N;
  port DPRAM_INT_N;
  port DPRAM_BUSY_N;
  port DPRAM_D;
  port DPRAM_A;
 
  virtual void Register() {
    reg ( HFL_A );
    reg ( HFL_OE_N );
    reg ( HFL_WE_N );
    reg ( HFL_SPARE );
    regb( FMD,  7, 0 );
    regb( FMA, 17, 0 );
 
    reg ( FINIT_N );
    reg ( FDONE );
    reg ( FPRGM_N );
    reg ( EFINIT_N );
    reg ( EFDONE );
    reg ( EFPRGM_N );
 
    reg ( DX );
    reg ( CLKX );
    reg ( CLKR );
    reg ( FSX );
 
    reg ( HPU_RESET_N );
    reg ( SOFTRESET_N );
    regb( INT, 2, 0 );
    reg ( INTREQ );
    reg ( INTPEND );
 
    reg ( FIFO_WEN_N );
    reg ( FIFO_PAF_N );
    reg ( FIFO_WR_CLK );
    regb( FIFO_D, 31, 0 );
 
    reg ( DPRAM_OE_N );
    reg ( DPRAM_CE_N );
    reg ( DPRAM_WE_N );
    reg ( DPRAM_INT_N );
    reg ( DPRAM_BUSY_N );
    regb( DPRAM_D, 31, 0 );
    regb( DPRAM_A, 14, 0 );
 
  }
};
 
class CM_VME_Interface : public TModule {
public:
// ***** member bundles ***** //
  CB_VME_CG        CG;
  CB_Front_VME     FP;
  CB_Host_VME      HO;
  CB_VME_JT        JT;
  CB_VME_PWR       PWR;
  CB_VMEbus        VMEbus;
 
// ***** member ports ***** //
  port GND;
  port MB_VCC;
  port MB_VCC5;
  port VPC;
 
// ***** member modules and parts ***** //
  CM_VMEBuffers     buffers;
  CM_VMEC_PLD       VMEC_PLD;
  CM_VMED_PLD       VMED_PLD;
  CM_STD_FIFO       VME_FIFO;
  CP_CY7C057V      VME_DPR;
 
 
  CM_FlashPLD     FlashPLD;
  CP_AM29LV033C  BootFlash;
  CP_AM29LV033C  CR_Flash;
 
  CP_EXB2HV222JV  PulldownDPRAM_Data;
  CP_EXB2HV222JV  PullupDIPSW[ 4 ];    // 2.2K pullups for DIP switches and GA_N
 
// decoupling
/* Decoupling Counts:
VCC:
   VMEC_PLD:       cdc: 4    tdc: 1
   VMED_PLD:       cdc: 4    tdc: 0   (shares TDC with VMEC_PLD)
   Flash PLD:      cdc: 4    tdc: 1
   Dual-Port RAM:  cdc: 7    tdc: 0   (shares TDC with FIFO)
   BootFlash:      cdc: 2    tdc: 0   (shares TDC with Flash PLD)
   CR_Flash:       cdc: 2    tdc: 0   (added later, so in separate array)
   FIFO:         ( cdc: 11   tdc: 1   )  <-- already included in CM_STD_FIFO
VCC5:
   Buffers:        cdc: 4x6 + 2   tdc: 1x5 + 2
*/
    enum { vcc_cdc_count  = 21,
           vcc5_cdc_count = 26,
           vcc_tdc_count  = 2,
           vcc5_tdc_count = 3 };
    CP_CDC_POS  VCC_CDC[  vcc_cdc_count  ];    // ceramic decoupling
    CP_CDC_POS  VCC5_CDC[ vcc5_cdc_count ];
    CP_TDC_POS  VCC_TDC[  vcc_tdc_count  ];    // tantalum decoupling
    CP_TDC_POS  VCC5_TDC[ vcc5_tdc_count ];
 
    CP_CDC_POS  CR_CDC[ 2 ];    // ceramic decoupling for CR flash, which was added after layout started
 
  virtual void Register() {  //Register function
// bundles
    reg( CG );
    reg( FP );
    reg( HO );
    reg( JT );
    reg( PWR );
    reg( VMEbus );
 
// ports
    reg ( GND );
    reg ( MB_VCC );
    reg ( MB_VCC5 );
    reg ( VPC );
 
// parts and modules
    reg( buffers );
    reg( VMEC_PLD );
    reg( VMED_PLD );
    reg( VME_FIFO );
    reg( VME_DPR );
 
    reg( FlashPLD  );
    reg( BootFlash );
    reg( CR_Flash  );
 
    reg(  PulldownDPRAM_Data );
    rega( PullupDIPSW, 4 );
 
    rega( VCC_CDC,  vcc_cdc_count  );
    rega( VCC5_CDC, vcc5_cdc_count );
    rega( VCC_TDC,  vcc_tdc_count  );
    rega( VCC5_TDC, vcc5_tdc_count );
    rega( CR_CDC,   2              );
  }
 
  virtual void Connect() {  //Connect function
 
    wireall( GND );              // Power
    wireall( MB_VCC, "VCC" );
    wireall( MB_VCC5, "VCC5" );
    wire   ( VPC );
 
    //Connections to ports
    wireall( GND, "BM" );
    GND     <<  VME_DPR.SIZE    <<  VME_DPR.BA      <<  VME_DPR.WA;
    GND     <<  VME_DPR.B_N(0)  <<  VME_DPR.B_N(1)  <<  VME_DPR.B_N(2)  <<  VME_DPR.B_N(3);
    MB_VCC  <<  VME_DPR.CE1L    <<  VME_DPR.CE1R    <<  VME_DPR.M_S     <<  VME_FIFO.LD_N;
 
    //Connect JTAG
    JT.VMEC_PLD       << VMEC_PLD.JT;
    JT.VMED_PLD       << VMED_PLD.JT;
    JT.FlashPLD       << FlashPLD.JT;
 
    CG.VME_CLK( 0 )   << VMEC_PLD.CLKIN;
    CG.VME_CLK( 1 )   << VMED_PLD.CLKIN;
    CG.VME_CLK( 2 )   << VME_FIFO.RD_CLK;
 
    CG.SOFTRESET_N       << FlashPLD.SOFTRESET_N;  // soft reset to CG PLD's
    HO.SOFTRESET_N       << FlashPLD.SOFTRESET_N;
 
 
    //Power Control Connections
    "SYSRESET_N"       << FlashPLD.SYSRESET_N   << buffers.SYSRESET_N;    // to flash PLD, which may forward it to motherboard power supervisor chip
    PWR                << FlashPLD.PwrCtrl;
    PWR.HARDRESET_N    << VMEC_PLD.HARDRESET_N   // from motherboard power supervisor chip
                       << VMED_PLD.HARDRESET_N;  // only FlashPLD, VMEC_PLD, and VMED_PLD get HARDRESET_N--all others get SOFTRESET_N
 
    //VME Bus Connections
    VMEbus.D          << buffers.VMED;
    VMEbus.A          << buffers.VMEA(31, 1);
    VMEbus.LWORD_N    << buffers.VMEA(0);
    VMEbus.DTACK_N    << buffers.VME_DTACK_N;
    VMEbus.BERR_N     << buffers.VME_BERR_N;
    VMEbus.AS_N       << buffers.VME_AS_N;
    VMEbus.DS0_N      << buffers.VME_DS0_N;
    VMEbus.DS1_N      << buffers.VME_DS1_N;
    VMEbus.WRITE_N    << buffers.VME_WRITE_N;
    VMEbus.IACK_N     << buffers.VME_IACK_N;
    VMEbus.IACKIN_N   << buffers.VME_IACKIN_N;
    VMEbus.IACKOUT_N  << buffers.VME_IACKOUT_N;
    VMEbus.AM         << buffers.VME_AM;
    VMEbus.IRQ        << buffers.VME_IRQ;
    VMEbus.GA_N       << VMEC_PLD.GA_N
                      << FlashPLD.GA_N;          // see below for GA_N pullup resistors
    VMEbus.SYSRESET_N << buffers.VME_SYSRESET_N;
 
    FP << FlashPLD.FP;   // Front panel connnections to FlashPLD
 
// pullups for DIP switches and GA_N's
    for ( int i = 0; i < 4; ++ i ) {
      merge( MB_VCC, PullupDIPSW[ i ].B );
      "/NC"  <<      PullupDIPSW[ i ].A( 2 );  // three resistors per pack are not used
      "/NC"  <<      PullupDIPSW[ i ].A( 4 );
      "/NC"  <<      PullupDIPSW[ i ].A( 6 );
    }
 
    int ai = 0;                       // resistor index:  0, 1, 3, 5, 7
    for ( int i = 0; i < 5; ++i ) {
      FP.DIPSW0_(  i )  <<  PullupDIPSW[ 0 ].A( ai );
      FP.DIPSW1_(  i )  <<  PullupDIPSW[ 1 ].A( ai );
      FP.DIPSW2_(  i )  <<  PullupDIPSW[ 2 ].A( ai );
      VMEbus.GA_N( i )  <<  PullupDIPSW[ 3 ].A( ai );   // GA_N's are connected to VMEC_PLD and FlashPLD --> two loads
      i ? ai += 2 : ai += 1;    // increment ai by two, except first time
    }
 
    //Connect Flash Memory controls, address and data
    HO.HFL_A             <<  FlashPLD.HFL_A;
    HO.HFL_OE_N          <<  FlashPLD.HFL_OE_N;
    HO.HFL_WE_N          <<  FlashPLD.HFL_WE_N;
    HO.HFL_SPARE         <<  FlashPLD.HFL_SPARE;
 
    HO.FMA               <<  FlashPLD.FMA(17, 0);
    "FMA"                <<  FlashPLD.FMA(21, 0);    // for readable net name (though FMA17-FMA0 will be overridden by higher-level net name (BA))
    FlashPLD.FMA(21, 0)                    <<  BootFlash.A(21, 0);
    HO.FMD               <<  FlashPLD.FMD  <<  BootFlash.DQ;
 
 
    //Connect FPGA Configuration Signals
    HO.FINIT_N    <<  FlashPLD.HFINIT_N;
    HO.FDONE      <<  FlashPLD.HFDONE;
    JT.CCLK       <<  FlashPLD.CCLK;       // CM_JTAG buffers and distributes CCLK and DIN
    JT.DIN        <<  FlashPLD.DIN;
    HO.FPRGM_N    <<  FlashPLD.HFPRGM_N;
    HO.EFINIT_N   <<  FlashPLD.HEFINIT_N;
    HO.EFDONE     <<  FlashPLD.HEFDONE;
    HO.EFPRGM_N   <<  FlashPLD.HEFPRGM_N;
 
 
    //Connect Host DSP Serial Port
    HO.DX           << FlashPLD.HSPDX;
    HO.CLKX         << FlashPLD.HSPCLKX;
    HO.CLKR         << FlashPLD.HSPCLKR;
    HO.FSX          << FlashPLD.HSPFSX;
 
    //Connect Host Reset line
    HO.HPU_RESET_N  << FlashPLD.HPU_RESET_N;
 
    //Connect Host->VME Interrupt
    "INTREQ"   << HO.INTREQ       << VMEC_PLD.INTREQ;
    "INT"      << HO.INT          << VMEC_PLD.INT;
    "INTPEND"  << HO.INTPEND      << VMEC_PLD.INTPEND;
 
    //Connect Host FIFO Signals
    "WEN_N"    << HO.FIFO_WEN_N   << VME_FIFO.WEN_N;
    "PAF_N"    << HO.FIFO_PAF_N   << VME_FIFO.PAF_N;
    "WR_CLK"   << HO.FIFO_WR_CLK  << VME_FIFO.WR_CLK;
    "FIFO_D"   << HO.FIFO_D       << VME_FIFO.D;
 
    "VME_FIFO_MRS_N"  <<  VME_FIFO.MRS_N  <<  FlashPLD.VME_FIFO_MRS_N;
 
    "VMEC_GEN" << FlashPLD.VMEC_GEN << VMEC_PLD.VMEC_GEN;
 
 
    //Connect Host to Dual-Port RAM
    "DPRAM_A"   << HO.DPRAM_A      << VME_DPR.A_L;
    "DPRAM_D"   << HO.DPRAM_D      << VME_DPR.IO_L(31, 0);
    "DPRL_OE_N" << HO.DPRAM_OE_N   << VME_DPR.OEL_N;
    "DPRL_CE_N" << HO.DPRAM_CE_N   << VME_DPR.CE0L_N;
    "DPRL_WE_N" << HO.DPRAM_WE_N   << VME_DPR.R_WL;
    "INT_N"     << HO.DPRAM_INT_N  << VME_DPR.INTL_N;
    "BUSY_N"    << HO.DPRAM_BUSY_N << VME_DPR.BUSYL_N;
 
    FlashPLD.BOOT_CLK << CG.BOOT_CLK;
 
    //Upper 4 bits of Data lines on VME Dual-Port RAM need to be Pulled Down since not being used
    "UNUSED_DPR_IO_R" << VME_DPR.IO_R( 35, 32 );  // for readable net names
    "UNUSED_DPR_IO_L" << VME_DPR.IO_L( 35, 32 );
 
    merge( GND, PulldownDPRAM_Data.A );
    for( int i = 0; i < 4; i++ ) {
      PulldownDPRAM_Data.B( i   ) <<  VME_DPR.IO_R( 35-i );
      PulldownDPRAM_Data.B( i+4 ) <<  VME_DPR.IO_L( 35-i );
    }
 
 
    //Internal connections
    "LD"    <<  VMED_PLD.LD     <<  VME_FIFO.Q( 31, 0 )  <<  VME_DPR.IO_R( 31, 0 );
    "LDBW"  <<  VMEC_PLD.FMLD   <<  VMED_PLD.LDBW  << FlashPLD.LD << CR_Flash.DQ;  // separate byte-wide LD bus
    "LA"    <<  VMEC_PLD.LA     <<  VME_DPR.A_R( 14, 0);
 
    VMEC_PLD.LA( 16, 14 )       <<  FlashPLD.VFL_A( 4, 2 );   // Flash PLD gets some MSB's
    VMEC_PLD.LA(  3,  2 )       <<  FlashPLD.VFL_A( 1, 0 );   // and some LSB's (e.g., for addressing VME CSR's)
 
 
    "D"            << VMED_PLD.D( 31, 0)      << buffers.D(31, 0);   // buffered VME data
    "A"            << buffers.A(31,  0)       << VMED_PLD.A(31, 0);  // buffered VME address
                      buffers.A(31,  1)       << VMEC_PLD.A(31, 1);
 
    "LWORD_N"      << buffers.A(    0)        << VMEC_PLD.LWORD_N;
 
    "AM"           << buffers.AM(5, 0)        << VMEC_PLD.AM(5, 0);
    "AS_N"         << buffers.AS_N            << VMEC_PLD.AS_N;
    "DS0_N"        << buffers.DS0_N           << VMEC_PLD.DS0_N;
    "DS1_N"        << buffers.DS1_N           << VMEC_PLD.DS1_N;
    "WRITE_N"      << buffers.WRITE_N         << VMEC_PLD.WRITE_N;
    "IACK_N"       << buffers.IACK_N          << VMEC_PLD.IACK_N;
    "IACKIN_N"     << buffers.IACKIN_N        << VMEC_PLD.IACKIN_N;
    "DTACK_N"      << buffers.DTACK_N         << VMEC_PLD.DTACK_N;
    "BERR_N"       << buffers.BERR_N          << VMEC_PLD.BERR_N       <<  FlashPLD.BERR_N;
    "IACKOUT_N"    << buffers.IACKOUT_N       << VMEC_PLD.IACKOUT_N;
    "IRQ"          << buffers.IRQ(7, 1)       << VMEC_PLD.IRQ(7, 1);
    "DBUFOE_N"     << buffers.DBUFOE_N        << VMEC_PLD.DBUFOE_N;
    "DBUFDIR"      << buffers.DBUFDIR         << VMEC_PLD.DBUFDIR;
    "ABUFDIR"      << buffers.ABUFDIR         << VMEC_PLD.ABUFDIR;
    "ABUFOE_N"     << buffers.ABUFOE_N        << VMEC_PLD.ABUFOE_N;
    "IBUFOE_N"     << buffers.IBUFOE_N        << VMEC_PLD.IBUFOE_N;
 
    "VMEDOE_N"     << VMEC_PLD.VMEDOE_N       << VMED_PLD.VMEDOE_N;
    "VMEAOE_N"     << VMEC_PLD.VMEAOE_N       << VMED_PLD.VMEAOE_N;
    "VADDRCLKEN_N" << VMEC_PLD.VADDRCLKEN_N   << VMED_PLD.VADDRCLKEN_N;
    "VDATACLKEN_N" << VMEC_PLD.VDATACLKEN_N   << VMED_PLD.VDATACLKEN_N;
    "VASEL"        << VMEC_PLD.VASEL          << VMED_PLD.VASEL;
    "VLDSEL"       << VMEC_PLD.VLDSEL         << VMED_PLD.VLDSEL;
    "LDOE_N"       << VMEC_PLD.LDOE_N         << VMED_PLD.LDOE_N;
    "RW_N"         << VMEC_PLD.RW_N           << VMED_PLD.RW_N;
 
    "DPCE_N"       << VMEC_PLD.DPCE_N         << VME_DPR.CE0R_N;
    "DPBSY_N"      << VMEC_PLD.DPBSY_N        << VME_DPR.BUSYR_N;
    "VMEOE_N"      << VMEC_PLD.OE_N           << VME_DPR.OER_N;
                      VMEC_PLD.OE_N           << FlashPLD.VFL_OE_N;
 
    "VFL_CE_N"     << VMEC_PLD.VFL_CE_N       << FlashPLD.VFL_CE_N;
 
    "FREN_N"       << VMEC_PLD.FREN_N         << VME_FIFO.REN_N;
    "FOE_N"        << VMEC_PLD.FOE_N          << VME_FIFO.OE_N;
    "FEF_N"        << VMEC_PLD.FEF_N          << VME_FIFO.EF_N;
 
    "VMEWE_N"      << VMEC_PLD.WE_N           << VME_DPR.R_WR;
                      VMEC_PLD.WE_N           << FlashPLD.VFL_WE_N;
 
    MB_VCC         << VME_DPR.SEML_N;
    MB_VCC         << VME_DPR.SEMR_N;
    "/NC"          << VME_DPR.INTR_N;
    "/NC"          << VME_FIFO.PAE_N;
 
 
 
// Added by S.Pier
    "/NC" << VMEbus.RESP_N;     // new for VME64 (formerly RESERVED), used by some 3U boards
 
    merge( "/NC", VMEbus.BGOUT_N );    // arbitration bus
    merge( "/NC", VMEbus.BGIN_N  );
    merge( "/NC", VMEbus.BR_N    );
    "/NC" << VMEbus.BBSY_N;
    "/NC" << VMEbus.BCLR_N;
 
    "/NC" << VMEbus.SYSCLK;     // utility bus
    "/NC" << VMEbus.ACFAIL_N;
    "/NC" << VMEbus.SYSFAIL_N;
    "/NC" << VMEbus.SERA;       // new for VME64 (formerly SERCLK)
    "/NC" << VMEbus.SERB;       // new for VME64 (formerly SERDAT*)
    "/NC" << VMEbus.LI_I_N;     // new for VME64: live insertion in and out
    "/NC" << VMEbus.LI_O_N;
 
    "/NC" << VMEbus.MPR;        // test and maintenance bus (reserved, new for VME64x)
    "/NC" << VMEbus.MCLK;
    "/NC" << VMEbus.MSD;
    "/NC" << VMEbus.MMD;
    "/NC" << VMEbus.MCTL;
 
    "/NC" << VMEbus.RETRY_N;    // no longer implemented in this design
 
    "/NC" << VMEbus.GAP_N;      // geographical address parity
 
    merge( "/NC", VMEbus.RSVBUS );  // reserved by VME standard
    merge( "/NC", VMEbus.RSVU   );
 
 
// Flash PLD, flash memory connections
    "FMCE_N"   <<  FlashPLD.FMCE_N      <<  BootFlash.CE_N;
    "FMOE_N"   <<  FlashPLD.FMOE_N      <<  BootFlash.OE_N;
    "FMWE_N"   <<  FlashPLD.FMWE_N      <<  BootFlash.WE_N;
                   FlashPLD.SOFTRESET_N <<  BootFlash.RESET_N;
 
    merge( GND,                              CR_Flash.A( 21, 15 ) );
                   VMEC_PLD.LA          <<   CR_Flash.A( 14,  0 );
    "CRCE_N"   <<  VMEC_PLD.CRCE_N      <<   CR_Flash.CE_N;
    "VMEOE_N"                           <<   CR_Flash.OE_N;
    "VMEWE_N"                           <<   CR_Flash.WE_N;
    PWR.HARDRESET_N                     <<   CR_Flash.RESET_N;
 
 
    MB_VCC    <<   CR_Flash.ACC;      // accelerated programming pin not used
    MB_VCC    <<  BootFlash.ACC;
    "/NC"     <<  BootFlash.RY_BY_N;  // ready/busy output (open drain) not used
    "/NC"     <<   CR_Flash.RY_BY_N;
 
    //Decoupling Connections
    for ( int i = 0; i < vcc_cdc_count; ++ i )   MB_VCC  << VCC_CDC[  i ].POS;
    for ( int i = 0; i < vcc_tdc_count; ++ i )   MB_VCC  << VCC_TDC[  i ].POS;
    for ( int i = 0; i < vcc5_cdc_count; ++ i )  MB_VCC5 << VCC5_CDC[ i ].POS;
    for ( int i = 0; i < vcc5_tdc_count; ++ i )  MB_VCC5 << VCC5_TDC[ i ].POS;
    for ( int i = 0; i < 2            ; ++ i )   MB_VCC  << CR_CDC[   i ].POS;
  }
};
 
#endif