CBOLD IROD Example Design: backplane.h

Coolquest, Inc.
C⁺⁺BOLD Example Design: IROD
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// THIS FILE IS IN THE PUBLIC DOMAIN.
// IT IS PROVIDED AS IS WITHOUT WARRANTY OF ANY KIND, EITHER EXPRESSED OR IMPLIED, INCLUDING, BUT
// NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE.
 
#ifndef _BackplaneH_
#define _BackplaneH_
 
#include "vme_connectors.h"
#include "rod_connectors.h"
#include "clock_generation.h"  // for CB_Back_CG
#include "data_exchange.h"     // for CB_Back_DX
#include "interconnect.h"      // for CB_Back_IC
 
 
// All necessary decoupling capacitors are already included.
 
// CM_Backplane: ROD backplane connectors
// Some signal names had to be changed from standard VME names--search
// for "VME name" in file VME_Connectors.pt for details.
 
 
// CB_Pwr_Back: Interface between Power and Backplane

class CB_PWR_Back : public TBundle {
public:
  port VPC;         // precharge needed by VME buffers (via series resistor)
  port VPOS3_3;     //  3.3V
  port VPOS5;       //  5  V
  port VPOS12;      // 12  V -- only used by CM_Measure
 
  virtual void Register() {
    reg( VPC );
    reg( VPOS3_3 );
    reg( VPOS5 );
    reg( VPOS12 );
  }
};
 
 
// CB_Host_BK: Interface between Host and Backplane
 
class CB_Host_BK : public TBundle {
public:
  port SOFTRESET_N;  // signals output directly to backplane
  port BUSY_N;
 
  virtual void Register() {
    reg( SOFTRESET_N );
    reg( BUSY_N );
  }
};
 
 
 
class CB_VMEbus : public TBundle {
public:
  port D;          // data transfer bus
  port A;
  port AM;
  port LWORD_N;
  port DS0_N;
  port DS1_N;
  port AS_N;
  port WRITE_N;
  port DTACK_N;
  port BERR_N;
  port RETRY_N;    // new for VME64 (formerly RESERVED)
  port RESP_N;     // new for VME64 (formerly RESERVED), used by some 3U boards
 
  port BGOUT_N;    // arbitration bus
  port BGIN_N;
  port BR_N;
  port BBSY_N;
  port BCLR_N;
 
  port IRQ;        // priority interrupt bus
  port IACK_N;
  port IACKIN_N;
  port IACKOUT_N;
 
  port SYSCLK;     // utility bus
  port ACFAIL_N;
  port SYSRESET_N;
  port SYSFAIL_N;
  port SERA;       // new for VME64 (formerly SERCLK)
  port SERB;       // new for VME64 (formerly SERDAT*)
  port LI_I_N;     // new for VME64: live insertion in and out
  port LI_O_N;
 
  port MPR;        // test and maintenance bus (reserved, new for VME64x)
  port MCLK;
  port MSD;
  port MMD;
  port MCTL;
 
  port GA_N;       // geographical address
  port GAP_N;      // geographical address parity
 
  port RSVBUS;     // reserved by VME standard, do not connect
  port RSVU;
 
 
  virtual void Register() {
    regb( D, 31, 0 );
    regb( A, 31, 1 );
    regb( AM, 5, 0 );
    reg( LWORD_N );
    reg( DS0_N );
    reg( DS1_N );
    reg( AS_N );
    reg( WRITE_N );
    reg( DTACK_N );
    reg( BERR_N );
    reg( RETRY_N );
    reg( RESP_N );
 
    regb( BGOUT_N, 3, 0 );
    regb( BGIN_N, 3, 0 );
    regb( BR_N, 3, 0 );
    reg( BBSY_N );
    reg( BCLR_N );
 
    regb( IRQ, 7, 1 );
    reg( IACK_N );
    reg( IACKIN_N );
    reg( IACKOUT_N );
 
    reg( SYSCLK );
    reg( ACFAIL_N );
    reg( SYSRESET_N );
    reg( SYSFAIL_N );
    reg( SERA );
    reg( SERB );
 
    reg( LI_I_N );
    reg( LI_O_N );
 
    reg( MPR );
    reg( MCLK );
    reg( MSD );
    reg( MMD );
    reg( MCTL );
 
    regb( GA_N, 4, 0 );
    reg(  GAP_N );
 
    regb( RSVBUS, 13, 0 );
    regb( RSVU,    1, 0 );
 
  }
};
 
 
class CM_Backplane : public TModule {    // Backplane Subsystem
public:
 
// ***** member bundles ***** //
  CB_PWR_Back    Power;     // interface to Power subsystem
  CB_VMEbus      VMEbus;    // standard VMEbus bundle
  CB_Back_CG     CG;        // interface to ClockGeneration
  CB_Back_DX     DX;        // interface to DataExchange
  CB_Host_BK     HO;        // interface to Host
  CB_Back_IC     IC;        // interface to Interconnect
  CB_Back_JT     JT;        // interface to JTAG
 
// ***** member ports ***** //
  port GND;
 
  port UD_A;
  port UD_C;
  port UD_Z;
  port UD_D;
 
 
// ***** member modules and parts ***** //
  CP_VME64_P1   BAP1;  // standard VME P1
  CP_VME64_P2R  BAP2;  // VME P2 with ROD-specific user-defined pins
  CP_ROD_J0P0   BAP0;  // ROD-specific versions of P0, P5, P6
  CP_ROD_J5P5   BAP5;
  CP_ROD_J6P6   BAP6;
 
  // decoupling (also important as signal return path )  >>> place near connectors as specified below
  enum { v5_cdc_count =  1      // >>> place near P1
                        +3      // >>> place near P2
                        +2      // >>> place near P5
                        +1,     // >>> place near P6
         v3_cdc_count =  3      // >>> place near P1
                        +2      // >>> place near P5
                        +2,     // >>> place near P6
         v5_tdc_count =  1,
         v3_tdc_count =  1 };
  CP_CDC_POS  V5_CDC[ v5_cdc_count ];    // ceramic decoupling
  CP_CDC_POS  V3_CDC[ v3_cdc_count ];
  CP_TDC_POS  V5_TDC[ v5_tdc_count ];    // tantalum decoupling
  CP_TDC_POS  V3_TDC[ v3_tdc_count ];
 
  virtual void Register() {
// bundles
    reg( Power  );
    reg( VMEbus );
    reg( CG );
    reg( DX );
    reg( HO );
    reg( IC );
    reg( JT );
 
// ports
    reg( GND );
 
// parts and modules
    reg( BAP1 );
    reg( BAP2 );
    reg( BAP0 );
    reg( BAP5 );
    reg( BAP6 );
 
    rega( V5_CDC, v5_cdc_count );
    rega( V3_CDC, v3_cdc_count );
    rega( V5_TDC, v5_tdc_count );
    rega( V3_TDC, v3_tdc_count );
  }
 
  virtual void Connect() {
    wire( Power,    BAP1 );
    wire( Power,    BAP2 );
    wire( Power,    BAP5 );
    wire( Power,    BAP6 );
    "/NC"        << BAP1.VNEG12;       // unused voltages
    "/NC"        << BAP1.VSTDBY5;
 
    "BPWR_POSV1" << BAP1.POSV1 << BAP0.POSV1;
    "BPWR_POSV2" << BAP1.POSV2 << BAP0.POSV2;
    "BPWR_NEGV1" << BAP1.NEGV1 << BAP0.NEGV1;
    "BPWR_NEGV2" << BAP1.NEGV2 << BAP0.NEGV2;
 
    for ( int i = 0; i < v5_cdc_count; ++ i )  Power.VPOS5    <<  V5_CDC[ i ].POS;
    for ( int i = 0; i < v3_cdc_count; ++ i )  Power.VPOS3_3  <<  V3_CDC[ i ].POS;
    for ( int i = 0; i < v5_tdc_count; ++ i )  Power.VPOS5    <<  V5_TDC[ i ].POS;
    for ( int i = 0; i < v3_tdc_count; ++ i )  Power.VPOS3_3  <<  V3_TDC[ i ].POS;
 
 
    wire( VMEbus, BAP1 );   // wire up all identically-named (and ranged) ports
    wire( VMEbus, BAP2 );
 
    HO.SOFTRESET_N  <<  BAP2.RESET_N;  // outputs to backplane
    HO.BUSY_N       <<  BAP5.BUSY_N;
 
    wire( CG, BAP0 );    // clocks to/from backplane
    wire( CG, BAP5 );
    wire( CG, BAP6 );
 
    wire( JT, BAP2 );    // JTAG and FPGA configuration to backplane
 
// backplane generics
    DX.DG                  << BAP0.DG;
 
    IC.TMP_N               << BAP2.TMP_N;
    IC.BG_B[ 0 ]           << BAP2.BG_B0;
    IC.BG_A[ 0 ]           << BAP2.BG_A0;
    IC.BG_B[ 1 ]( 15, 8 )  << BAP2.BG_B1( 15, 8 );
 
    IC.BG_B[ 1 ](  7, 0 )  << BAP5.BG_B1(  7, 0 );
    IC.BG_A[ 1 ]           << BAP5.BG_A1;
    IC.BG_B[ 2 ]           << BAP5.BG_B2;
    IC.BG_A[ 2 ]           << BAP5.BG_A2;
    IC.BG_B[ 3 ]           << BAP5.BG_B3;
 
    IC.BG_A[ 3 ]           << BAP6.BG_A3;
    IC.BG_B[ 4 ]           << BAP6.BG_B4;
    IC.BG_A[ 4 ]           << BAP6.BG_A4;
    IC.BG_B[ 5 ]           << BAP6.BG_B5;
    IC.BG_A[ 5 ]           << BAP6.BG_A5;
 
    IC.TG                  << BAP6.TG;
 
 
    "/NC"  << BAP0.NC;  // spares
    "/NC"  << BAP2.NC;
 
    VMEbus.D( 15,  0 ) << BAP1.D( 15,  0 );  // a few VMEbus ports are split between P1 and P2
    VMEbus.D( 31, 16 ) << BAP2.D( 31, 16 );
    VMEbus.A( 23,  1 ) << BAP1.A( 23,  1 );
    VMEbus.A( 31, 24 ) << BAP2.A( 31, 24 );
 
    wireall( GND );
  }
};
 
 
 
// CB_VME_Std_Power: VME standard voltages (not currently used for anything)
 
class CB_VME_Std_Power : public TBundle {
public:
  port VPC;
  port VSTDBY5;
  port VPOS3_3;
  port VPOS5;
  port VPOS12;
  port VNEG12;
  port POSV1;
  port POSV2;
  port NEGV1;
  port NEGV2;
 
  virtual void Register() {
    reg( VPC );
    reg( VSTDBY5 );
    reg( VPOS3_3 );
    reg( VPOS5 );
    reg( VPOS12 );
    reg( VNEG12 );
    reg( POSV1 );
    reg( POSV2 );
    reg( NEGV1 );
    reg( NEGV2 );
  }
};
 
#endif
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