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C++BOLD Example Design: IROD

// THIS FILE IS IN THE PUBLIC DOMAIN.
// IT IS PROVIDED AS IS WITHOUT WARRANTY OF ANY KIND, EITHER EXPRESSED OR IMPLIED, INCLUDING, BUT
// NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE.
 
#ifndef _FlashPLDH_
#define _FlashPLDH_
 
#include "xc95144xl_100.h"
#include "power.h"
#include "backplane.h"
#include "switches.h"
#include "leds.h"
#include "front_panel.h"  // for CB_Front_VME
 
class CM_FlashPLD : public TModule {
public:
// ***** member bundles ***** //
  CB_JTAG       JT;
  CB_VME_PWR    PwrCtrl;
  CB_Front_VME  FP;         // front panel connections passed through VME subsystem
 
 
// ***** member ports ***** //
  port VCC;           // Power and Ground
  port GND;
 
  port VMEC_GEN;        // general-purpose signals to VMEC PLD, e.g., used to disable VME in non-VME startup modes
  port VME_FIFO_MRS_N;  // VME FIFO can be reset under HPU control
  port GA_N;            // geographical address, readable by HPU, may be used during startup
 
  port BOOT_CLK;      // Clock used for HPU Bootup
  port SYSRESET_N;    // input:  reset from VMEbus, can be factored into MBPWR_MR_N, must be ignored in standalone mode
  port SOFTRESET_N;   // output: Software Reset, can be asserted/released by RCC or VME to hold Host and DPU's in reset
  port HPU_RESET_N;   // output: Holds Host Module in Reset, e.g., until FPGA is configured
 
  port LD;            // Local Data Bus (From VME)
  port VFL_A;             // 5 address bits from VME used to select internal registers, flash memory
  port VFL_CE_N;         // Flash Memory Chip Enable (From VME)
  port VFL_OE_N;         // Flash Memory Output Enable (From VME)
  port VFL_WE_N;         // Flash Memory Write Enable (From VME)
 
                      // From Host
  port HFL_A;         // address selects between FlashPLD internal registers and flash memory
  port HFL_OE_N;      // read strobe
  port HFL_WE_N;      // write strobe
  port HFL_SPARE;    // no current use
 
  port HSPDX;         //Host Serial Port General I/O Signals, used by the Host to configure FPGA's
  port HSPCLKX;
  port HSPCLKR;
  port HSPFSX;
 
  port CCLK;        //Configuration Clock to all FPGA's (buffered in CM_JTAG)
  port DIN;         //Configuration Data  to all FPGA's (buffered in CM_JTAG)
 
  port HEFPRGM_N;     //Host EMIF FPGA Program Signal
  port HEFINIT_N;     //Host EMIF FPGA Init Signal
  port HEFDONE;       //Host EMIF FPGA Done Signal
 
  port HFPRGM_N;      //Host XB FPGA Program Signal
  port HFINIT_N;      //Host XB FPGA Init Signal
  port HFDONE;        //Host XB FPGA Done Signal
 
  port FMCE_N;        //Flash Memory Chip Enable (To Flash Memory)
  port FMOE_N;        //Flash Memory Output Enable
  port FMWE_N;        //Flash Memory Write Enable (Guarded by jumper)
  port FMD;           //Flash Memory Data Bus (To Flash Memory)
  port FMA;           //Flash Memory Address Bus
 
  port BERR_N;        // VME bus error signal, connected to flash PLD so CSR register can be implemented in flash PLD
 
// ***** member modules and parts ***** //
  CP_XC95144XL_144    Cpld;
 
  virtual void Register() {
 
// bundles
    reg( JT );
    reg( PwrCtrl );
    reg( FP );
 
// ports
    reg ( VCC );
    reg ( GND );
 
    regb( VMEC_GEN, 1, 0 );
    reg(  VME_FIFO_MRS_N );
    regb( GA_N, 4, 0 );
 
    reg ( BOOT_CLK    );
    reg ( SYSRESET_N  );
    reg ( SOFTRESET_N );
    reg ( HPU_RESET_N );
 
    regb( LD, 7, 0 );
    regb( VFL_A, 4, 0 );
    reg ( VFL_CE_N );
    reg ( VFL_OE_N );
    reg ( VFL_WE_N );
 
    reg ( HFL_A );
    reg ( HFL_OE_N );
    reg ( HFL_WE_N );
    reg ( HFL_SPARE );
 
    reg ( HSPDX );
    reg ( HSPCLKX );
    reg ( HSPCLKR );
    reg ( HSPFSX );
 
    reg ( CCLK );
    reg ( DIN );
 
    reg ( HEFPRGM_N );
    reg ( HEFINIT_N );
    reg ( HEFDONE );
 
    reg ( HFPRGM_N );
    reg ( HFINIT_N );
    reg ( HFDONE );
 
    reg ( FMCE_N );
    reg ( FMOE_N );
    reg ( FMWE_N );
    regb( FMD, 7, 0 );
    regb( FMA, 21, 0 );
 
    reg ( BERR_N );
 
// parts and modules
    reg(  Cpld );
  }
 
  virtual void Connect() {  //Connect function
    //JTAG Connections
    wire   ( JT, Cpld );
 
    wire( VCC );              //Connect VCC to upper level
    wire( VCC, "VCCIO" );     // VCCIO is 3.3V for this application
    wire( GND );              // Connect GND to upper level
 
 
 
// Connections to PLD
    "/NC"             <<  Cpld.IO2_GTS3;
    "/NC"             <<  Cpld.IO3_GTS4;
 
    int i = 0;
    FP.DIPSW0_( i++ )  <<  Cpld.IO4;    // 15 DIP switch--pullup's in VME_Interface subsystem
    "/NC"             <<  Cpld.IO5_GTS1;
    "/NC"             <<  Cpld.IO6_GTS2;
    FP.DIPSW0_( i++ )  <<  Cpld.IO7;
    FP.DIPSW0_( i++ )  <<  Cpld.IO9;
    FP.DIPSW0_( i++ )  <<  Cpld.IO10;
    FP.DIPSW0_( i++ )  <<  Cpld.IO11;
 
    i = 0;
    FP.DIPSW1_( i++ )  <<  Cpld.IO12;
    FP.DIPSW1_( i++ )  <<  Cpld.IO13;
    FP.DIPSW1_( i++ )  <<  Cpld.IO14;
    FP.DIPSW1_( i++ )  <<  Cpld.IO15;
    FP.DIPSW1_( i++ )  <<  Cpld.IO16;
 
    i = 0;
    FP.DIPSW2_( i++ )  <<  Cpld.IO17;
    FP.DIPSW2_( i++ )  <<  Cpld.IO19;
    FP.DIPSW2_( i++ )  <<  Cpld.IO20;
    FP.DIPSW2_( i++ )  <<  Cpld.IO21;
    FP.DIPSW2_( i++ )  <<  Cpld.IO22;
 
    i = 0;
    GA_N( i++ )      <<  Cpld.IO23;  // 5 GA_N  (pullup located in VME_Interface subsystem)
    GA_N( i++ )      <<  Cpld.IO24;
    GA_N( i++ )      <<  Cpld.IO25;
    GA_N( i++ )      <<  Cpld.IO26;
    GA_N( i++ )      <<  Cpld.IO27;
 
    VME_FIFO_MRS_N   <<  Cpld.IO28;
    BOOT_CLK         <<  Cpld.IO30_GCK1;
    VMEC_GEN( 0 )    <<  Cpld.IO31;
    "/NC"            <<  Cpld.IO32_GCK2;
    VMEC_GEN( 1 )    <<  Cpld.IO33;
 
    PwrCtrl.ONE_MR_N     <<  Cpld.IO34;        // Power Control
    PwrCtrl.ONE_O        <<  Cpld.IO35;
    "/NC"                <<  Cpld.IO38_GCK3;
    PwrCtrl.PENA         <<  Cpld.IO39;
    PwrCtrl.PENC         <<  Cpld.IO40;
    PwrCtrl.PENB         <<  Cpld.IO41;
    PwrCtrl.PENB_SURGE   <<  Cpld.IO43;
    PwrCtrl.DSP_VAOK     <<  Cpld.IO44;
    PwrCtrl.VBOK         <<  Cpld.IO45;
    PwrCtrl.DSP_VCOK     <<  Cpld.IO46;
    VFL_A( 4 )           <<  Cpld.IO48;
    PwrCtrl.HARDRESET_N  <<  Cpld.IO143_GSR;
    PwrCtrl.MBPWR_MR_N   <<  Cpld.IO49;
 
    FP.LED_MB_VB    <<  Cpld.IO50;        // outputs to LED's in FrontPanel subsystem
    FP.LED_DSP_VB   <<  Cpld.IO51;
    FP.LED_DSP_VA   <<  Cpld.IO52;
    FP.LED_HPU0     <<  Cpld.IO53;
    FP.LED_HPU1     <<  Cpld.IO54;
    FP.LED_VME0     <<  Cpld.IO56;
    FP.LED_VME1     <<  Cpld.IO57;
 
    BERR_N       <<  Cpld.IO58;
    SYSRESET_N   <<  Cpld.IO59;
    SOFTRESET_N  <<  Cpld.IO60;
    HPU_RESET_N  <<  Cpld.IO61;
 
    VFL_A( 3)    <<  Cpld.IO64;
    VFL_A( 2)    <<  Cpld.IO66;
    VFL_A( 1)    <<  Cpld.IO68;
    VFL_A( 0)    <<  Cpld.IO69;
    VFL_CE_N     <<  Cpld.IO70;
    VFL_OE_N     <<  Cpld.IO71;
    VFL_WE_N     <<  Cpld.IO74;
 
    HFL_A        <<  Cpld.IO75;
    HFL_OE_N     <<  Cpld.IO76;
    HFL_WE_N     <<  Cpld.IO77;
    HFL_SPARE    <<  Cpld.IO78;
 
    HFINIT_N     <<  Cpld.IO79;
    HFDONE       <<  Cpld.IO80;
 
    HSPDX        <<  Cpld.IO81;
    HSPCLKX      <<  Cpld.IO82;
    HSPCLKR      <<  Cpld.IO83;
    HSPFSX       <<  Cpld.IO85;
 
    LD(0)  <<  Cpld.IO86;
    LD(1)  <<  Cpld.IO87;
    LD(2)  <<  Cpld.IO88;
    LD(3)  <<  Cpld.IO91;
    LD(4)  <<  Cpld.IO92;
    LD(5)  <<  Cpld.IO93;
    LD(6)  <<  Cpld.IO94;
    LD(7)  <<  Cpld.IO95;
 
    FMD(7)  <<  Cpld.IO96;
    FMD(6)  <<  Cpld.IO97;
    FMD(5)  <<  Cpld.IO98;
    FMD(4)  <<  Cpld.IO100;
    FMD(3)  <<  Cpld.IO101;
    FMD(2)  <<  Cpld.IO102;
    FMD(1)  <<  Cpld.IO103;
    FMD(0)  <<  Cpld.IO104;
 
    FMA(21)  <<  Cpld.IO105;
    FMA(20)  <<  Cpld.IO106;
    FMA(19)  <<  Cpld.IO107;
    FMA(18)  <<  Cpld.IO110;
    FMA(17)  <<  Cpld.IO111;
    FMA(16)  <<  Cpld.IO112;
    FMA(15)  <<  Cpld.IO113;
    FMA(14)  <<  Cpld.IO115;
    FMA(13)  <<  Cpld.IO116;
    FMA(12)  <<  Cpld.IO117;
    FMA(11)  <<  Cpld.IO118;
    FMA(10)  <<  Cpld.IO119;
    FMA(9)   <<  Cpld.IO120;
    FMA(8)   <<  Cpld.IO121;
    FMA(7)   <<  Cpld.IO124;
    FMA(6)   <<  Cpld.IO125;
    FMA(5)   <<  Cpld.IO126;
    FMA(4)   <<  Cpld.IO128;
    FMA(3)   <<  Cpld.IO129;
    FMA(2)   <<  Cpld.IO130;
    FMA(1)   <<  Cpld.IO131;
    FMA(0)   <<  Cpld.IO132;
 
    CCLK       <<  Cpld.IO133;
    DIN        <<  Cpld.IO134;
    HFPRGM_N     <<  Cpld.IO135;
    FMCE_N       <<  Cpld.IO136;
    FMOE_N       <<  Cpld.IO137;
    FMWE_N       <<  Cpld.IO138;
    HEFINIT_N    <<  Cpld.IO139;
    HEFDONE      <<  Cpld.IO140;
    HEFPRGM_N    <<  Cpld.IO142;
  }
};
 
#endif