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C++BOLD Example Design: IROD

// THIS FILE IS IN THE PUBLIC DOMAIN.
// IT IS PROVIDED AS IS WITHOUT WARRANTY OF ANY KIND, EITHER EXPRESSED OR IMPLIED, INCLUDING, BUT
// NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE.
 
#ifndef _HalfRODH_
#define _HalfRODH_
 
// get interfaces to other subsystems
#include "interconnect.h"
#include "dpu_control.h"
#include "clock_generation.h"
#include "data_exchange.h"
 
#include "gpu.h"
 
class CM_HalfROD : public TModule {    // six DPU's
public:
// ***** member bundles ***** //
  CB_Half_CG    CG;        // interface to ClockGeneration
  CB_Half_DC    DC;        // interface to DPU Control
  CB_Half_DX    DX;        // interface to DataExchange
  CB_Half_IC    IC;        // interface to Interconnect
  CB_Half_JT    JT;        // interface to JTAG
 
// ***** member ports ***** //
  port DSP_VCC;    // VCC:  3.3 V
  port DSP_VB;     // VB, typical use:  2.5 V for FPGA VCCINT
  port DSP_VA;     // VA, typical use:  1.8 V for DSP VCORE
  port GND;
 
 
// ***** member modules and parts ***** //
  CM_DPU  DPU[ DPU_HalfCount ];
 
// decoupling (more decoupling is in CM_GPU and on the GPU board itself)
  enum { vc_tdc_count =  1,
         vb_tdc_count =  1,
         va_tdc_count =  1 };
  CP_TDC_POS  VC_TDC[ vc_tdc_count ];    // tantalum decoupling
  CP_TDC_POS  VB_TDC[ vb_tdc_count ];
  CP_TDC_POS  VA_TDC[ va_tdc_count ];
 
 
  virtual void Register() {
// bundles
    reg( CG );
    reg( DC );
    reg( DX );
    reg( IC );
    reg( JT );
 
// ports
    reg( DSP_VCC );
    reg( DSP_VB );
    reg( DSP_VA );
    reg( GND );
 
// parts and modules    
    rega( DPU, DPU_HalfCount );
    for ( int i = 0; i < DPU_HalfCount; ++ i ) {    // assign separate reference base to each DPU
      DPU[ i ].SetReferenceBase( CSTRING( i ) );
    }
    rega( VC_TDC, vc_tdc_count );
    rega( VB_TDC, vb_tdc_count );
    rega( VA_TDC, va_tdc_count );
  }
 
  virtual void Connect() {
    wireall( DSP_VCC );
    wireall( DSP_VB );
    wireall( DSP_VA );
    wireall( GND );
 
// decoupling
    for ( int i = 0; i < vc_tdc_count; ++ i )  DSP_VCC << VC_TDC[ i ].POS;
    for ( int i = 0; i < vb_tdc_count; ++ i )  DSP_VB  << VB_TDC[ i ].POS;
    for ( int i = 0; i < va_tdc_count; ++ i )  DSP_VA  << VA_TDC[ i ].POS;
 
 
// ID straps
    for ( int i = 0; i < DPU_HalfCount; ++ i ) {
      for ( int s = 0; s < 3; ++ s ) {                                // for each bit in ID
        if ( i  &  ( 1 << s ) )   DPU[ i ].STRAP( s )  <<  DSP_VCC;   // if bit is a 1
        else                      DPU[ i ].STRAP( s )  <<  GND;       // if bit is a 0
      }
    }
 
 
// clocks
    for ( int i = 0; i < DPU_HalfCount; ++ i ) {
      CG.DC_CLK(  i )  <<  DPU[ i ].Clocks.DC_CLK;       // RCLK, DC_CLK: one clock per DPU
      CG.RCLK(    i )  <<  DPU[ i ].Clocks.RCLK;
      CG.DPU_CLK( i )  <<  DPU[ i ].Clocks.CLKIN;        // DPU_CLK, SCLK, DX_CLK: some are shared, see CM_ClockGeneration
      CG.SCLK(    i )  <<  DPU[ i ].Clocks.SCLK;
      CG.DX_CLK(  i )  <<  DPU[ i ].Clocks.DX_CLK;
    }
 
 
// all else
    for ( int i = 0; i < DPU_HalfCount; ++ i ) {
      DC               <<  DPU[ i ].DC;
      DX               <<  DPU[ i ].DX;
      IC.IC_BUS        <<  DPU[ i ].IC_BUS;  // bussed connections to all DPU's
      IC.IC_DPU[ i ]   <<  DPU[ i ].IC_DPU;  // pt-to-pt connections to each DPU
      JT.EMU[    i ]   <<  DPU[ i ].Emulator;
      JT.CONF[   i ]   <<  DPU[ i ].CONF;
    }
  }
};
 
#endif